126.96.36.199. XAUI PHY Register Interface and Register Descriptions
The Avalon® memory-mapped interface PHY management provides access to the XAUI PHY IP core PCS, PMA, and transceiver reconfiguration registers.
Avalon® memory-mapped interface clock input.
|phy_mgmt_clk_reset||Input||Global reset signal that resets the entire XAUI PHY. This signal is active high and level sensitive.|
|phy_mgmt_addr[8:0]||Input||9-bit Avalon® memory-mapped interface address.|
|phy_mgmt_writedata[31:0]||Input||32-bit input data.|
|phy_mgmt_readdata[31:0]||Output||32-bit output data.|
|phy_mgmt_write||Input||Write signal. Asserted high.|
|phy_mgmt_read||Input||Read signal. Asserted high.|
|phy_mgmt_waitrequest||Output||When asserted, indicates that the Avalon® memory-mapped interface slave is unable to respond to a read or write request. When asserted, control signals to the Avalon® memory-mapped interface slave must remain constant.|
For more information about the Avalon® memory-mapped interface, including timing diagrams, refer to the Avalon Interface Specification.
The following table specifies the registers that you can access using the Avalon® memory-mapped interface PHY management using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.
|Word Addr||Bits||R/W||Register Name||Description|
|Reset Control Registers–Automatic Reset Controller|
Bit mask for reset registers at addresses 0x042 and 0x044. The default value is all 1s. You can reset channel < n > when bit< n > = 1.
|0x042||[1:0]||W||reset_control(write)||Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. This bit self-clears.|
|R||reset_status(read)||Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit. This bit self-clears.|
|Reset Controls –Manual Mode|
|0x044||[31:4,0]||RW||Reserved||It is safe to write 0s to reserved bits.|
|||RW||reset_tx_digital||Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.|
|||RW||reset_rx_analog||Writing a 1 causes the internal RX analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.|
|||RW||reset_rx_digital||Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.|
|PMA Control and Status Registers|
|0x061||[31:0]||RW||phy_serial_loopback||Writing a 1 to channel < n > puts channel < n > in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback Modes.|
|0x064||[31:0]||RW||pma_rx_set_locktodata||When set, programs the RX CDR PLL to lock to the incoming data. Bit < n > corresponds to channel < n >.|
|0x065||[31:0]||RW||pma_rx_set_locktoref||When set, programs the RX CDR PLL to lock to the reference clock. Bit < n > corresponds to channel < n >.|
|0x066||[31:0]||RO||pma_rx_is_lockedtodata||When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit < n > corresponds to channel < n >.|
|0x067||[31:0]||RO||pma_rx_is_lockedtoref||When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n > corresponds to channel < n >.|
Records the synchronization status of the corresponding bit. The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link; soft XAUI uses bits 0–3. Reading the value of the syncstatus register clears the bits.
From block: Word aligner
When set, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. Use errdetect with disperr to differentiate between a code violation error, a disparity error, or both. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect register clears the bits.
From block: 8B/10B decoder
Indicates that the received 10-bit code or data group has a disparity error. When set, the corresponding errdetect bits are also set. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect register clears the bits.
From block: 8B/10B decoder
|0x08a||||RW||simulation_flag||Setting this bit to 1 shortens the duration of reset and loss timer when simulating. Intel recommends that you keep this bit set for simulation.|
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