Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents XAUI PHY Register Interface and Register Descriptions

The Avalon® memory-mapped interface PHY management provides access to the XAUI PHY IP core PCS, PMA, and transceiver reconfiguration registers.

Table 179.  Signals in the Avalon® Memory-Mapped Interface PHY management
Signal Name Direction Description
phy_mgmt_clk Input

Avalon® memory-mapped interface clock input.

phy_mgmt_clk_reset Input Global reset signal that resets the entire XAUI PHY. This signal is active high and level sensitive.
phy_mgmt_addr[8:0] Input 9-bit Avalon® memory-mapped interface address.
phy_mgmt_writedata[31:0] Input 32-bit input data.