Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

2.6.4.7.4. Arria 10 GMII PCS Registers

Addr Bit R/W Name Description
0x490 9 RW RESTART_AUTO_ NEGOTIATION Set this bit to 1 to restart the Clause 37 auto-negotiation (AN) sequence. For normal operation, set this bit to the default 0 value. This bit is self-clearing.
12 RW AUTO_NEGOTIATION_ ENABLE Set this bit to 1 to enable Clause 37 AN. The default value is 1.
15 RW Reset Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines, comma detection function, and the 8B/10B encoder and decoder. For normal operation, set this bit to 0. This bit self clears.
0x491 2 R LINK_STATUS A value of 1 indicates that a valid link is operating. A value of 0 indicates an invalid link. If link synchronization is lost, this bit is 0.