Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.6.4.7.4. Arria 10 GMII PCS Registers

Addr Bit R/W Name Description
0x490 9 RW RESTART_AUTO_ NEGOTIATION Set this bit to 1 to restart the Clause 37 auto-negotiation (AN) sequence. For normal operation, set this bit to the default 0 value. This bit is self-clearing.
12 RW AUTO_NEGOTIATION_ ENABLE Set this bit to 1 to enable Clause 37 AN. The default value is 1.
15 RW Reset Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines, comma detection function, and the 8B/10B encoder and decoder. For normal operation, set this bit to 0. This bit self clears.
0x491 2 R LINK_STATUS A value of 1 indicates that a valid link is operating. A value of 0 indicates an invalid link. If link synchronization is lost, this bit is 0.
3 R AUTO_NEGOTIATION_ ABILITY A value of 1 indicates that the PCS function supports Clause 37 AN.
5 R AUTO_NEGOTIATION_ COMPLETE A value of 1 indicates the following status:
  • The AN process is complete.
  • The AN control registers are valid.
0x494 (1000BASE-X mode) 5 RW FD Full-duplex mode enable for the local device. Set to 1 for full-duplex support.
6 RW HD Half-duplex mode enable for the local device. Set to 1 for half-duplex support. This bit should always be set to 0 for the KR PHY IP.
8:7 RW PS2,PS1 Pause support for the local device. The following encodings are defined for PS1/PS2:
  • PS1=0 / PS2=0: Pause is not supported
  • PS1=0 / PS2=1: Asymmetric pause toward link partner
  • PS1=1 / PS2=0: Symmetric pause
  • PS1=1 / PS2=1: Pause is supported on TX and RX
13:12 RW RF2,RF1 Remote fault condition for local device. The following encodings are defined for RF1/RF2:
  • RF1=0 / RF2=0: No error, link is valid (reset condition)
  • RF1=0 / RF2=1: Offline
  • RF1=1 / RF2=0: Failure condition
  • RF1=1 / RF2=1: AN error
14 R0 ACK Acknowledge for local device. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
15 RW NP Next page. In the device ability register, this bit is always set to 0.
0x495 (1000BASE-X mode) 5 R FD Full-duplex mode enable for the link partner. This bit must be 1 because only full duplex is supported.
6 R HD Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit must be 0 because half-duplex mode is not supported.
8:7 R PS2,PS1 Specifies pause support for link partner. The following encodings are defined for PS1/PS2:
  • PS1=0 / PS2=0: Pause is not supported
  • PS1=0 / PS2=1: Asymmetric pause toward link partner
  • PS1=1 / PS2=0: Symmetric pause
  • PS1=1 / PS2=1: Pause is supported on TX and RX
13:12 R RF2,RF1 Remote fault condition for link partner. The following encodings are defined for RF1/RF2:
  • RF1=0 / RF2=0: No error, link is valid (reset condition)
  • RF1=0 / RF2=1: Offline
  • RF1=1 / RF2=0: Failure condition
  • RF1=1 / RF2=1: AN error
14 R ACK Acknowledge for link partner. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
15 R NP Next page. In link partner register. When set to 0, the link partner has a Next Page to send. When set to 1, the link partner does not send a Next Page. Next Page is not supported in AN.
0x494 (SGMII mode) 14 RO ACK Local device acknowledge. Value as specified in IEEE 802.3z standard.
0x495 (SGMII mode) 11:10 RO Speed[1:0]

Link partner speed:

  • 00: copper interface speed is 10 Mbps
  • 01: copper interface speed is 100 Mbps
  • 10: copper interface speed is 1 Gigabit
  • 11: reserved
12 RO COPPER_DUPLEX_STATUS Link partner capability:
  • 1: copper interface is capable of full-duplex operation
  • 0: copper interface is capable of half-duplex operation
Note: The PHY IP Core does not support half duplex operation because it is not supported in SGMII mode of the 1G/10G PHY IP core.
14 RO ACK

Link partner acknowledge. Value as specified in IEEE 802.3z standard.

15 RO COPPER_LINK_STATUS Link partner status:
  • 1: copper interface link is up
  • 0: copper interface link is down
0x496 0 R LINK_PARTNER_AUTO_NEGOTIATION_ABLE Set to 1, indicates that the link partner supports AN. The default value is 0.
1 R PAGE_RECEIVE A value of 1 indicates that a new page has been received with new partner ability available in the register partner ability. The default value is 0 when the system management agent performs a read access.
0x4A2 15:0 RW Link timer[15:0] Low-order 16 bits of the 21-bit auto-negotiation link timer. Each timer step corresponds to 8 ns (assuming a 125 MHz clock). The total timer corresponds to 16 ms. The reset value sets the timer to 10 ms for hardware mode and 10 us for simulation mode.
0x4A3 4:0 RW Link timer[20:16] High-order 5 bits of the 21-bit auto-negotiation link timer.
0x4A4 0 RW SGMII_ENA Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode.
1 RW USE_SGMII_AN

In SGMII mode, setting this bit to 1b'1 configures the PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the SGMII_SPEED and SGMII_DUPLEX bits.

3:2 RW SGMII_SPEED

SGMII speed. When the PCS operates in SGMII mode (SGMII_ENA = 1) and is not programmed for automatic configuration (USE_SGMII_AN = 0), the following encodings specify the speed :

  • 2'b00: 10 Mbps
  • 2'b01: 100 Mbps
  • 2'b10: Gigabit
  • 2'b11: Reserved

These bits are not used when SGMII_ENA = 0or USE_SGMII_AN = 1.

4 RW SGMII half-duplex When set to 1, enables half-duplex mode for 10/100 Mbps speed. This bit is ignored when SGMII_ENA = 0 or USE_SGMII_AN = 1. These bits are only valid when you enable the SGMII mode only and not the clause-37 auto-negotiation mode.

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