9.2.1. Enabling Transceiver Toolkit Support
|Enable Dynamic Reconfiguration||Allows you to change the configuration of the transceiver channels and PLLs without powering down the device.|
|Enable Native PHY Debug Master Endpoint (NPDME)||Allows you to access the transceiver and PLL registers through System Console. When you recompile your design, the Intel® Quartus® Prime software inserts the NPDME debug fabric and embedded logic.|
|Enable control and status registers||Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.|
|Enable PRBS Soft Accumulators||Enables soft logic for performing PRBS bit and error accumulation when you use the hard PRBS generator and checker.|
|Enable capability registers||Enables capability registers that provide high-level information about the configuration of the transceiver channel.|
|IP Core||Parameter to Enable|
|Transceiver ATX PLL Intel FPGA IP||
|CMU PLL Intel FPGA IP|
|fPLL Intel FPGA IP|
The following figures illustrate the parameters that you must enable to debug transceivers in Intel® Arria® 10 GX transceiver designs.
You can either activate these settings when you first instantiate these components or modify the instances after preliminary compilation. Follow these steps for each transceiver IP core:
- In the IP Components tab of the Project Navigator, right click the IP instance, and click Edit in Parameter Editor.
- Turn on debug settings.
Refer to the Dynamic Reconfiguration Parameters in Intel® Arria® 10 GX Transceiver Native PHY IP Core and Dynamic Reconfiguration Parameters in Intel® Arria® 10 GX Transceiver ATX PLL Core diagrams.
- Connect the reference signals that the debugging logic requires, if applicable.
The NDPME requires connections for clock and reset signals. For details about frequency requirements, refer to the Ports and Parameters section.
- Click Generate HDL.
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