Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

9.2.1. Enabling Transceiver Toolkit Support

To enable Intel® Arria® 10 transceiver toolkit support, you must enable the following parameters in the Transceiver Native PHY and Transceiver PLL IP cores.
Table 332.  Parameters to Enable Transceiver Toolkit Support in Transceiver Native PHY IP Core
Parameter Description
Enable Dynamic Reconfiguration Allows you to change the configuration of the transceiver channels and PLLs without powering down the device.
Enable Native PHY Debug Master Endpoint (NPDME) Allows you to access the transceiver and PLL registers through System Console. When you recompile your design, the Intel® Quartus® Prime software inserts the NPDME debug fabric and embedded logic.
Enable control and status registers Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS Soft Accumulators Enables soft logic for performing PRBS bit and error accumulation when you use the hard PRBS generator and checker.
Enable capability registers Enables capability registers that provide high-level information about the configuration of the transceiver channel.
Table 333.  Parameters to Enable Transceiver Toolkit Support in Transceiver PLL IP Core</