Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface

Use the Avalon® memory-mapped interface PHY management to read the state of the optional PMA control and status signals available in the XAUI PHY IP core registers. In some cases you may need to know the instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core.

Table 178.  Optional Control and Status Signals—Soft IP Implementation
Signal Name Direction Description
rx_channelaligned Output When asserted, indicates that all 4 RX channels are aligned. Synchronous to mgmt_clk. This signal is asserted when the RX lanes are fully aligned and ready to receive data.
rx_disperr[7:0] Output Received 10-bit code or data group has a disparity error. It is paired with rx_errdetect which is also asserted when a disparity error occurs. The rx_disperr signal is 2 bits wide per channel for a total of 8 bits per XAUI link. Synchronous to mgmt_clk.
rx_errdetect[7:0] Output When asserted, indicates an 8B/10B code group violation. It is asserted if the received 10-bit code group has a code violation or disparity error. Use rx_errdetect with the rx_disperr signal to differentiate between a code violation error, a disparity error, or both. The rx_errdetect signal is 2 bits wide per channel for a total of 8 bits per XAUI link. Synchronous to mgmt_clk.
rx_syncstatus[7:0] Output Synchronization indication. RX synchronization is indicated on the rx_syncstatus port of each channel. The rx_syncstatus signal is 2 bits per channel for a total of 8 bits per hard XAUI link. The rx_syncstatus signal is 1 bit per channel for a total of 4 bits per soft XAUI link. Synchronous to mgmt_clk.

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