Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.2.2.10.2. Register Mode

The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock.

In Register mode, rx_parallel_data (data), rx_control indicates whether rx_parallel_data is a data or control word, and rx_enh_data_valid (data valid) are registered at the FIFO output. The RX FIFO in register mode has one register stage or one parallel clock latency.

Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of 32 words under the following conditions:
  • When the Enhanced PCS RX FIFO is set to register mode.
  • When using the recovered clock to drive the core logics.
  • When there is no soft FIFO being generated along with the IP Catalog.

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