Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.5. Intel® Arria® 10 Transceiver PHY Architecture Revision History

Document Version Changes

2020.05.15

Made the following change:
  • Removed OFF as an option in the "Transmitter Buffer" figure and Programmable Transmitter On-Chip Termination (OCT).
2020.05.08 Made the following change:
  • Added the receiver pin I/O standards.
2019.11.04 Made the following changes to How to Enable CTLE and DFE:
  • Changed step #1 to, "Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0]."
  • Changed step #5 to, "Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]."
2018.06.15

Made the following changes:

  • Changed the AC gain settings for high bandwidth and medium bandwidth mode in the "High Gain Mode" section.
  • Added a note about bit slipping to the "RX Gearbox, RX Bitslip, and Polarity Inversion" section.
  • Clarified the description of DC gain circuitry in the "Continuous Time Linear Equalization (CTLE)" section.
  • Clarified the description of CTLE manual mode in the "High Data Rate Mode" section.
  • Removed the Channel Loss Compensation column from the "Pre-Emphasis Taps" table.
  • Updated Serial Loopback Path and Reverse Serial Loopback Path/Pre CDR figures and their notes.
  • Changed the instruction in step 1 of the "How to Enable CTLE and DFE" section.
2016.10.31

Made the following changes:

  • Added a note below the diagram "Diagnostic Loopback Path/Pre CDR" saying "TX pre-emp is not supported in pre-CDR loopback. TX pre-emp is recommended to set to zero for all taps."
  • "Idle OS Deletion" description updated to "Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the rx_enh_fifo_pfull flag deasserts".
  • Removed square wave pattern generator.
2015.05.02

Made the following changes:

  • Updated the configuration methods for the CTLE,and DFE schemes in the Arria 10 PMA Architecture section.
  • Removed a signal in the "Gen3 PCS Block Diagram" in the Arria 10 PCI Express Architecture section.
2015.12.18

Made the following changes:

  • Updated the configuration methods for the CTLE, DFE, and adaptation schemes in the Arria 10 PMA Architecture section.
2015.11.02

Made the following changes to the PMA Architecture section:

  • Updated "Channel Pulse Response" figure in the Decision Feedback Equalization (DFE) section.
  • Updated the value for the "Number of fixed DFE taps" in the Equalization table in the PMA Parameters section.

Made the following changes to the Enhanced PCS Architecture section:

  • Updated Phase Compensation Mode and Basic Mode sections.
  • Added 64B/66B Encoder Reset Condition section.
  • Updated TX Gearbox, TX Bitslip and Polarity Inversion sections.
  • Updated RX Bitslip in RX Gearbox, RX Bitslip, and Polarity Inversion figure.
  • Added “block synchronization” in Enhanced PCS introduction note.
  • Updated Enhanced PCS TX FIFO section.
  • Updated reference link for TX Phase Compensation Mode section.
  • Updated TX Register Mode description.
  • Updated Interlaken Frame Generator section description.
  • Updated 64B/66B Encoder and Transmitter State Machine section title.
  • Updated PRBS Pattern Generator (Shared between Enhanced and Standard) title
  • Updated Square Wave Pattern Generator (Shared between Enhanced and Standard)
  • Updated RX Register Mode description.

Made the following changes to the Standard PCS Architecture section:

  • Updated the Byte Serializer section for Serialize x2 and x4 modes.
  • Added new figures for 8B/10B Encoder Bit and Byte Reversal features.
2015.05.11

Made the following changes to the PMA Architecture section:

  • Updated link to XCVR_A10_RX_TERM_SEL in the "Transmitter Buffer".

  • Updated ODI vertical steps to 63 (0 and +/-32) in the "Receiver Buffer".

  • Updated CTLE section for adaptation modes. Moved CTLE in the "How to Enable CTLE and DFE" section.
  • Updated VGA section for adaptation modes.
  • Updated DFE section for adaptation modes. Moved DFE to the new "How to Enable CTLE and DFE" section.
  • Removed Triggered DFE mode.
  • Removed all references related to floating taps.

Made the following changes to the Enhanced PCS Architecture section:

  • Updated pattern generators (PRBS, Square Wave and PRP), PRBS Checker and PRP Verifier sections.
  • Revised the descriptions of TX FIFO Fast Register Mode.
  • Changed the title and descriptions in "Enhanced PCS Pattern Generators".
  • Added new sections for "PRBS Pattern Generator (Shared between Enhanced and Standard PCSes)", "Square Wave Pattern Generator (Shared between Enhanced and Standard PCSes)", and "Pseudo-Random Pattern Generator."
  • Changed sub title "PRBS Verifier" to "PRBS Checker" and changed their descriptions.
  • Changed descriptions in "PRP Verifier".
2014.12.15

Made the following changes to the Enhanced PCS Architecture section:

  • Added PRBS7 Generator to support 64-bit width only.
  • Updated the rule for tx_enh_data_valid control signal when TX FIFO is used in phase compensation mode.

Made the following changes to the PCI Express Gen3 PCS Architecture section:

  • Updated TX FIFO in Transmitter Datapath.
  • Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.

Made the following changes to the Standard PCS Architecture section:

  • Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.

Made the following changes to the PMA Architecture section:

  • Added High Speed Differential I/O and Power Distribution Network to the Transmitter Buffer circuitry.
  • Added Power Distribution Network induced Inter-Symbol Interference compensation.
  • Replaced the figures related to Programmable Pre Emphasis with a link to Pre Emphasis and Output Swing Settings Estimator.
2014.08.15

Made the following changes to the PCI Express Gen3 PCS Architecture section:

  • Corrected the low latency mode cycles of latency in the TX FIFO (Shared with Standard and Enhanced PCS).

Made the following changes to the Standard PCS Architecture section:

  • Removed the features not supported by 8B/10B Decoder.
  • Changed the description of TX FIFO to include the depth of the TX FIFO.
  • Updated the description of Polarity Inversion feature to include how to enable Polarity Inversion.
  • Updated the description of Pseudo-Random Binary Sequence (PRBS) Generator on the supported PCS-PMA interface widths.
  • Changed the value for Supported Word Aligner Pattern Lengths for Bitslip Mode when the PCS-PMA Interface Width is 8 in Table 5-8 Word Aligner Pattern Length for Various Word Aligner Modes.
  • Changed the description of RX FIFO to include the depth of the RX FIFO.
  • Changed the RX Word Aligner pattern length for PCS-PMA interface width 8 in Bitslip Mode.

Made the following changes to the Enhanced PCS Architecture section:

  • Changed references from MegaWizard to Parameters Editor.

Made the following changes to the PMA Architecture section:

  • Added 2nd post-tap and pre-tap Pre-Emphasis signals .
  • Updated DFE and CTLE modes of operation and Use Models.
  • Added new sections on How to Enable CTLE and How to Enable DFE.
  • Changed max data rate for GT channels to 25.8 Gbps in the Receiver Buffer CTLE section.
  • Updated Receiver Buffer figure by adding and modifying Adaptive Parametric Tuning Engine to include CDR and DFE.
  • Updated VGA section that includes VGA Frequency response for different gain settings.
2013.12.02 Initial release.

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