Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
Give Feedback

5.5. Intel® Arria® 10 Transceiver PHY Architecture Revision History

Document Version Changes


Made the following change:
  • Removed OFF as an option in the "Transmitter Buffer" figure and Programmable Transmitter On-Chip Termination (OCT).
2020.05.08 Made the following change:
  • Added the receiver pin I/O standards.
2019.11.04 Made the following changes to How to Enable CTLE and DFE:
  • Changed step #1 to, "Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0]."
  • Changed step #5 to, "Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]."

Made the following changes: