Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)

The RX FIFO interfaces between the PCS on the receiver side and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric and the PCS on the receiver side. The RX FIFO has a depth of 8. It operates in register FIFO and low latency modes.

Figure 265. RX FIFO Block Diagram


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