Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.7.6. fPLL IP Parameter Core Settings for PIPE

Table 189.  Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modesThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/Gen2 speeds)
PLL
General
fPLL mode Transceiver Transceiver Transceiver
Protocol Mode PCIe* Gen 1 PCIe Gen 2 PCIe Gen 2
Message level for rule violation Error Error Error
Number of PLL reference clocks 1 1 1
Selected reference clock source 0 0 0
Enable fractional mode Disable Disable Disable
Enable manual counter configuration Disable Disable Disable
Enable ATX to fPLL cascade clock input port Disable Disable Disable
Settings
Bandwidth Low, Medium, High Low, Medium, High Low, Medium, High
Feedback
Operation mode Direct Direct Direct
Output frequency
Transceiver usage
PLL output frequency 250oMHz 2500MHz 2500MHz
PLL datarate 2500Mbps 5000Mbps 5000Mbps
PLL integer reference clock frequency 100 MHz, 125 MHZ 100 MHz, 125 MHZ 100 MHz, 125 MHZ
Master Clock Generation Block (MCGB)
Include master clock generation block

Disable for x1

Enable for x2, x4, x8

Disable for x1

Enable for x2, x4, x8

Disable for x1

Disable for x2, x4, x8
Clock division factor

N/A for x1

1 for x2, x4, x8

N/A for x1

1 for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
Enable x6/xN non-bonded high-speed clock output port

N/A for x1

Disable for x2, x4, x8

N/A for x1

Disable for x2, x4, x8

N/A for x1

N/A for x2,x4, x8
Enable PCIe clock switch interface

N/A for x1

Disable for x2, x4, x8

N/A for x1

Enable for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
Number of auxiliary MCGB clock input ports

N/A for x1

0 for x2, x4, x8

N/A for x1

0 for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
MCGB input clock frequency 1250MHz 2500MHz 2500MHz
MCGB output data rate 2500Mbps 5000Mbps 5000Mbps
Bonding
Enable bonding clock output ports

N/A for x1 design

Enable for x2, x4, x8

N/A for x1 design

Enable for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
Enable feedback compensation bonding

N/A for x1 design

Disable for x2, x4, x8

N/A for x1 design

Disable for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
PMA interface width

N/A for x1 design

10 for x2, x4, x8

N/A for x1 design

10 for x2, x4, x8

N/A for x1

N/A for x2, x4, x8
Dynamic Reconfiguration
Enable dynamic reconfiguration Disable Disable Disable
Enable Native PHY Debug Master Endpoint Disable Disable Disable
Separate avmm_busy from reconfig_waitrequest N/A N/A N/A
Optional Reconfiguration Logic
Enable capability registers N/A N/A N/A
Set user-defined IP identifier N/A N/A N/A
Enable control and status registers N/A N/A N/A
Configuration Files
Configuration file prefix N/A N/A N/A
Generate SystemVerilog package file N/A N/A N/A
Generate C Header file N/A N/A N/A
Generate MIF (Memory Initialize file) N/A N/A N/A
Generation Options
Generate parameter documentation file Enable Enable Enable

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