Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

2.7.6. fPLL IP Parameter Core Settings for PIPE

Table 189.  Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modesThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/Gen2 speeds)
PLL
General
fPLL mode Transceiver Transceiver Transceiver
Protocol Mode PCIe* Gen 1 PCIe Gen 2 PCIe Gen 2
Message level for rule violation Error Error Error
Number of PLL reference clocks 1 1 1
Selected reference clock source 0 0