2.2.3. Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
- Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
- In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
- Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
- In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.
- Click Generate.
The Quartus® Prime software generates a <phy ip instance name> folder, <phy ip instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design files used for simulation and compilation.
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