Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.2.3. Generate the PHY IP Core

After configuring the PHY IP, complete the following steps to generate the PHY IP.

  1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
  2. In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
  3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
  4. In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.
  5. Click Generate.

The Quartus® Prime software generates a <phy ip in