Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Table 217.  General and Datapath Options Parameters
Parameter Range
Message level for rule violations

error

warning

Transceiver configuration rules

Basic/Custom (Standard PCS)

Basic/Custom w/Rate Match (Standard PCS)

PMA configuration rules

basic

Transceiver mode

TX/RX Duplex

TX Simplex

RX Simplex

Number of data channels 1 to 96
Data rate 611 Mbps to 12 Gbps
Enable datapath and interface reconfiguration On/Off
Enable simplified data interface On/Off
Table 218.  TX PMA Parameters
Parameter Range
TX channel bonding mode

Not bonded

PMA-only bonding

PMA and PCS bonding

PCS TX channel bonding master

Auto, n-1 (where n = the number of data channels)

Actual PCS TX channel bonding master

n-1 (where n = the number of data channels)

TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0 (Depends on the Number of TX PLL clock inputs per channel value)
Enable tx_pma_clkout port On/Off
Enable tx_pma_div_clkout port On/Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On/Off
Enable tx_pma_qpipullup port (QPI) On/Off
Enable tx_pma_qpipulldn port (QPI) On/Off
Enable tx_pma_txdetectrx port (QPI) On/Off
Enable tx_pma_rxfound port (QPI) On/Off
Enable rx_seriallpbken port On/Off
Table 219.  RX PMA Parameters
Parameter Range
Number of CDR reference clocks 1, 2, 3, 4, 5
Selected CDR reference clock 0, 1, 2, 3, 4
Selected CDR reference clock frequency Legal range defined by Quartus Prime software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
DFE adaptation mode disabled
Number of fixed dfe taps 3, 7
Enable rx_pma_clkout port On/Off
Enable rx_pma_div_clkout port On/Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 50, 66
Enable rx_pma_clkslip port On/Off
Enable rx_pma_qpipulldn port (QPI) On/Off
Enable rx_is_lockedtodata port On/Off
Enable rx_is_lockedtoref port On/Off
Enable rx_set_locktodata and rx_set_locktoref ports On/Off
Enable rx_seriallpbken port On/Off
Enable PRBS verifier control and status ports On/Off
Table 220.  Standard PCS Parameters
Parameter Range
Standard PCS / PMA interface width 8, 10, 16, 20
FPGA fabric / Standard TX PCS interface width 8, 10, 16, 20, 32, 40
FPGA fabric / Standard RX PCS interface width 8, 10, 16, 20, 32, 40
Enable 'Standard PCS' low latency mode

On/Off

Off (for Basic with Rate Match)

TX FIFO mode

low_latency

register_fifo

fast_register

RX FIFO Mode

low_latency

register_fifo

Enable tx_std_pcfifo_full port On/Off
Enable tx_std_pcfifo_empty port On/Off
Enable rx_std_pcfifo_full port On/Off
Enable rx_std_pcfifo_empty port On/Off
TX byte serializer mode

Disabled

Serialize x2

Serialize x4

RX byte deserializer mode

Disabled

Deserialize x2

Deserialize x4

Enable TX 8B/10B encoder On/Off
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On/Off
RX rate match FIFO mode

Disabled

Basic 10-bit PMA (for Basic with Rate Match)

Basic 20-bit PMA (for Basic with Rate Match)

RX rate match insert/delete -ve pattern (hex) User-defined value
RX rate match insert/delete +ve pattern (hex) User-defined value
Enable rx_std_rmfifo_full port On/Off
Enable rx_std_rmfifo_empty port On/Off
PCI Express* Gen 3 rate match FIFO mode Bypass
Enable TX bit slip On/Off
Enable tx_std_bitslipboundarysel port On/Off
RX word aligner mode

bitslip

manual (PLD controlled)

synchronous state machine

RX word aligner pattern length 7, 8, 10, 16, 20, 32, 40
RX word aligner pattern (hex) User-defined value
Number of word alignment patterns to achieve sync 0-255
Number of invalid data words to lose sync 0-63
Number of valid data words to decrement error count 0-255
Enable fast sync status reporting for deterministic latency SM On/Off
Enable rx_std_wa_patternalign port On/Off
Enable rx_std_wa_a1a2size port On/Off
Enable rx_std_bitslipboundarysel port On/Off
Enable rx_bitslip port On/Off
Enable TX bit reversal On/Off
Enable TX byte reversal On/Off
Enable TX polarity inversion On/Off
Enable tx_polinv port On/Off
Enable RX bit reversal On/Off
Enable rx_std_bitrev_ena port On/Off
Enable RX byte reversal On/Off
Enable rx_std_byterev_ena port On/Off
Enable RX polarity inversion On/Off
Enable rx_polinv port On/Off
Enable rx_std_signaldetect port On/Off
Enable PCIe* dynamic datarate switch ports Off
Enable PCIe pipe_hclk_in and pipe_hclk_out ports Off
Enable PCIe Gen 3 analog control ports Off
Enable PCIe electrical idle control and status ports Off
Enable PCIe pipe_rx_polarity port Off
Table 221.  Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration On/Off
Share reconfiguration interface On/Off
Enable Native PHY Debug Master Endpoint On/Off
Table 222.  Generation Options Parameters
Parameter Range
Generate parameter documentation file On/Off

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