Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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3.2.1. Dedicated Reference Clock Pins

To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL) can source the input reference clock directly from the reference clock buffer without passing through the reference clock network. The input reference clock is also fed into the reference clock network.

Figure 174. Dedicated Reference Clock PinsThere are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL, fPLL, and CMU PLL. The top refclk pin feeds the top ATX PLL, fPLL, and CMU PLL. The dedicated reference clock pins can also drive the reference clock network.

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