Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

8.5.1.2. XCVR_A10_RX_EQ_DC_GAIN_TRIM

Pin planner or Assignment Editor Name

Receiver High Gain Mode Equalizer DC Gain Control

Description

Controls the DC gain of the continuous time linear equalizer (CTLE) in high gain mode. A higher gain setting results in a larger DC gain.

For RX_LINK=SR, the default value is STG2_GAIN7.

For RX_LINK=LR, and if equalization mode = S1_MODE, default value of DC gain is STG1_GAIN7.

For RX_LINK=LR, and if equalization mode = NON_S1_MODE, default value of DC gain is NO_DC_GAIN.

For PCIe*, default value is NO_DC_GAIN.

For datarate > 17.4 Gbps, default value is NO_DC_GAIN.

Table 310.  Available Options
Value in TTK Value in Assignment Editor / qsf 67 Description
DC Gain 0 NO_DC_GAIN No DC gain
DC Gain 1 STG1_GAIN7 Equalizer DC gain setting 7
DC Gain 2 STG2_GAIN7 Equalizer DC gain setting 14
DC Gain 3 STG3_GAIN7 Equalizer DC gain setting 21
DC Gain 4 STG4_GAIN7 Equalizer DC gain setting 28

Assign To

RX serial data pin.

Syntax

set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM <value> -to <rx_serial_data pin name>

67 Refer to Intel® Arria® 10 Device Datasheet.

Did you find the information on this page useful?

Characters remaining:

Feedback Message