Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers

You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture, and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE 1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.

You must design your own MAC and other layers in the FPGA to implement the 10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver Configuration Rule using the Native PHY IP.

  1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
    Refer to Select and Instantiate the PHY IP Core for more details.
  2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the Transceiver configuration rule list located under Datapath Options, depending on which protocol you are implementing.
  3. Use the parameter values in the tables in Transceiver Native PHY Parameters for the 10GBASE-R Protocol as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets. Select 10GBASE-R Register Mode for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet your specific requirements.
  4. Click Generate to generate the Native PHY IP core RTL file.
    Figure 60. Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FECGenerating the IP core creates signals and ports based on your parameter settings.


  5. Instantiate and configure your PLL.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Arria 10 Transceiver Native PHY Reset Controller IP.
  7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
    Figure 61. Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
    Figure 62. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
  8. Simulate your design to verify its functionality.

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