Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

1.1.3. Arria® 10 GX and GT Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express* Hard IP blocks for Arria® 10 GX and GT devices.
Table 3.   Package Details for GX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device
  • Package U19: 19mm x 19mm package; 484 pins.
  • Package F27: 27mm x 27mm package; 672 pins.
  • Package F29: 29mm x 29mm package; 780 pins.
  • Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
  • Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
Device U19 F27 F29 F34 F35 K F40 N F40
Transceiver Count, PCIe* Hard IP Block Count
GX 016 6, 1 12, 1 12, 1
GX 022 6, 1 12, 1 12, 1
GX 027 12, 1 12, 1 24, 2 24, 2
GX 032 12, 1 12, 1 24, 2 24, 2
GX 048 12, 1 24, 2 36, 2
GX 057 24, 2 36, 2 36, 2 48, 2
GX 066 24, 2 36, 2 36, 2 48, 2
GX 090 24, 2 48, 2
GX 115 24, 2 48, 2
Table 4.   Package Details for GX and GT Devices with Transceivers and Hard IP Blocks Located on the Left and Right Side Periphery of the Device
  • Package F40: 40 mm x 40 mm package size; 1517 pins. R = 66 transceiver channels.
  • Package F45: 45mm x 45mm package size; 1932 pins. N = 48 transceiver channels, S = 72 transceiver channels, U = 96 transceiver channels.
  • If you're using GT transceivers in bank GXBL1E, the nth adjacent PCIe Hard IP block cannot be used.
Device R F40 N F45 S F45 U F45
Transceiver Count, PCIe Hard IP Block Count
GX 090 66, 3 48, 4 72, 4 96, 4
GX 115 66, 3 48, 4 72, 4 96, 4
GT 090 72, 4  
GT 115 72, 4  

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