Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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4.4.3. Transceiver PHY Reset Controller Interfaces

This section describes the top-level signals for the Transceiver PHY Reset Controller IP core.

The following figure illustrates the top-level signals of the Transceiver PHY Reset Controller IP core. Many of the signals in the figure become buses if you choose separate reset controls. The variables in the figure represent the following parameters:

  • <n>—The number of lanes
  • <p>—The number of PLLs
Figure 218. Transceiver PHY Reset Controller IP Core Top-Level SignalsGenerating the IP core creates signals and ports based on your parameter settings.


Note: PLL control is available when you enable the Expose Port parameter.
Table 248.  Top-Level SignalsThis table describes the signals in the above figure in the order that they are shown in the figure.
Signal Name Direction Clock Domain Description
pll_locked[<p>-1:0] Input Asynchronous Provides the PLL locked status input from each PLL. When asserted, indicates that the TX PLL is locked. When deasserted, the PLL is not locked. There is one signal per PLL.
pll_select[<p*n>-1:0] Input Synchronous to the Transceiver PHY Reset Controller input clock. Set to zero when not using multiple PLLs. When you select Use separate TX reset per channel, this bus provides enough inputs to specify an index for each pll_locked signal to listen to for each channel. When Use separate TX reset per channel is disabled, the pll_select signal is used for all channels.

n=1 when a single TX reset sequence is used for all channels.

tx_cal_busy[<n> -1:0] Input Asynchronous

This is the calibration status signal that results from the logical OR of pll_cal_busy and tx_cal_busy signals. The signal goes high when either the TX PLL or Transceiver PHY initial calibration is active. It is not asserted if you manually re-trigger the calibration IP. The signal goes low when calibration is completed. This signal gates the TX reset sequence. The width of this signals depends on the number of TX channels.

rx_cal_busy[<n> -1:0] Input Asynchronous This is calibration status signal from the Transceiver PHY IP core. When asserted, the initial calibration is active. When deasserted, calibration has completed. This signal gates the RX reset sequence. The width of this signals depends on the number of RX channels.
rx_is_lockedtodata [<n>-1:0] Input Synchronous to CDR Provides the rx_is_lockedtodata status from each RX CDR. When asserted, indicates that a particular RX CDR is ready to receive input data. If you do not choose separate controls for the RX channels, these inputs are ANDed together internally to provide a single status signal.
tx_manual[<n>-1:0] Input Asynchronous This optional signal places tx_digitalreset controller under automatic or manual control. When asserted, the associated tx_digitalreset controller logic does not automatically respond to deassertion of the pll_locked signal. However, the initial tx_digitalreset sequence still requires a one-time rising edge on pll_locked before proceeding. When deasserted, the associated tx_digitalreset controller automatically begins its reset sequence whenever the selected pll_locked signal is deasserted.
rx_manual[<n> -1:0] Input Asynchronous This optional signal places rx_digitalreset logic controller under automatic or manual control. In manual mode, the rx_digitalreset controller does not respond to the assertion or deassertion of the rx_is_lockedtodata signal. The rx_digitalreset controller asserts rx_ready when the rx_is_lockedtodata signal is asserted.
clock Input N/A A free running system clock input to the Transceiver PHY Reset Controller from which all internal logic is driven. If a free running clock is not available, hold reset until the system clock is stable.
reset Input Asynchronous Asynchronous reset input to the Transceiver PHY Reset Controller. When asserted, all configured reset outputs are asserted. Holding the reset input signal asserted holds all other reset outputs asserted. An option is available to synchronize with the system clock. In synchronous mode, the reset signal needs to stay asserted for at least (2) clock cycles by default.
tx_digitalreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Digital reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when any of the following conditions is true:
  • reset is asserted
  • pll_powerdown is asserted
  • pll_cal_busy is asserted
  • tx_cal_busy is asserted
  • PLL has not reached the initial lock (pll_locked deasserted)
  • pll_locked is deasserted and tx_manual is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of tx_digitalreset.
tx_analogreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock.

Analog reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when reset is asserted.

This signal follows pll_powerdown, which is deasserted after pll_locked goes high.

tx_ready[<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Status signal to indicate when the TX reset sequence is complete. This signal is deasserted while the TX reset is active. It is asserted a few clock cycles after the deassertion of tx_digitalreset. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of TX channels.
rx_digitalreset [<n> -1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Digital reset for RX. The width of this signal depends on the number of channels. This signal is asserted when any of the following conditions is true:
  • reset is asserted
  • rx_analogreset is asserted
  • rx_cal_busy is asserted
  • rx_is_lockedtodata is deasserted and rx_manual is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of rx_digitalreset.
rx_analogreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock.

Analog reset for RX. When asserted, resets the RX CDR and the RX PMA blocks of the transceiver PHY. This signal is asserted when any of the following conditions is true:

  • reset is asserted
  • rx_cal_busy is asserted

The width of this signal depends on the number of channels.

rx_ready[<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Status signal to indicate when the RX reset sequence is complete. This signal is deasserted while the RX reset is active. It is asserted a few clock cycles after the deassertion of rx_digitalreset. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of RX channels.
pll_powerdown[<p>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Asserted to power down a transceiver PLL circuit. When asserted, the selected TX PLL is reset.

Usage Examples for pll_select

  • If a single channel can switch between three TX PLLs, the pll_select signal indicates which one of the selected three TX PLL's pll_locked signal is used to communicate the PLL lock status to the TX reset sequence. In this case, to select the 3-bits wide pll_locked port, the pll_select port is 2-bits wide.
  • If three channels are instantiated with three TX PLLs and with a separate TX reset sequence per channel, the pll_select field is 6-bits wide (2-bits per channel). In this case, pll_select [1:0] represents channel 0, pll_select[3:2] represents channel 1, and pll_select[5:4] represents channel 2. For each channel, a separate pll_locked signal indicates the PLL lock status.
  • If three channels are instantiated with three TX PLLs and with a single TX reset sequence for all three channels, then pll_select field is 2-bits wide. In this case, the same pll_locked signal indicates the PLL lock status for all three channels.
  • If one channel is instantiated with one TX PLL, pll_select field is 1-bit wide. Connect pll_select to logic 0.
  • If three channels are instantiated with only one TX PLL and with a separate TX reset sequence per channel, the pll_select field is 3-bits wide. In this case, pll_select should be set to 0 since there is only one TX PLL available.

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