Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

4.4.3. Transceiver PHY Reset Controller Interfaces

This section describes the top-level signals for the Transceiver PHY Reset Controller IP core.

The following figure illustrates the top-level signals of the Transceiver PHY Reset Controller IP core. Many of the signals in the figure become buses if you choose separate reset controls. The variables in the figure represent the following parameters:

  • <n>—The number of lanes
  • <p>—The number of PLLs
Figure 218. Transceiver PHY Reset Controller IP Core Top-Level SignalsGenerating the IP core creates signals and ports based on your parameter settings.

Note: PLL control is available when you enable the Expose Port parameter.