Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

1.4. Intel® Arria® 10 Transceiver PHY Overview Revision History

Document Version Changes
2018.06.15 Made the following changes:
  • Changed the data rate range for the Standard PCS in the "PCS types Supported by GX Transceiver Channels" table.
2016.05.02 Made the following changes:
  • Maximum backplane rate updated from 16.0 Gbps to 12.5 Gbps.
  • No Backplane support when VCCR/T_GXB=0.95 (Low Power Mode).
  • Added a footnote to refer to Arria 10 Device datasheet for PCS Types Supported by GX and GT Transceiver Channels.
2016.02.11 Made the following changes:
  • Changed the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks" figure.
  • Changed the "GT Transceiver Bank Architecture" figure.
  • Added the "GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H" figure.
2015.11.02 Made the following changes:
  • Changed the minimum data rate from 611 Mbps to 1.0 Gbps.
  • Changed the location of a PCIe Hard IP block in the "Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP Blocks" figure.
2015.05.11 Changed lower limit of supported data rate from 1.0 Gbps to 611 Mbps
2014.12.15 Made the following changes:
  • Added statement that a 125-Mbps data rate is possible with oversampling in the "Arria 10 Transceiver PHY Overview" section.
  • Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types Supported by GX Transceiver Channels" table.
  • Changed the note in "The GX Transceiver Channel" section.
  • Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types and Data Rates Supported by GT Channel Configurations" table.
  • Added a legend entry to the "Arria 10 GT Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks" figure.
  • Added a legend entry to the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks" figure.
  • Added a legend entry to the "Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks" figure.
  • Changed the note to the "PCS Types and Data Rates Supported by GT Channel Configurations" table.
  • Changed the Data Rates Supported for GT channel Standard PCS and PCIe Gen3 PCS types in the "PCS Types and Data Rates Supported by GT Channel Configurations" table.
  • Added a related link to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines in the "Calibration" section.
2014.08.15 Made the following changes:
  • Changed the maximum data rate for GT channels to 25.8 Gbps.
  • Changed minimum data rate supported by GT transceiver channels to 1 Gbps from 611 Mbps.
  • Changed the figure "Arria 10 GX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to adda a clarification about PCIe Hard IP block.
  • Updated the legend for all figures in "Arria 10 GT Device Transceiver Layout" section.
  • Changed the device package names in Table1-3 and Table 1-4 in "Arria 10 GX and GT Device Package Details Section."
  • Updated figure "Arria 10 SX Device with 48,36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks.
  • Updated figure "Arria 10 SX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to add a clarification about PCIe Hard IP.
  • Updated the device package names in Table 1-5 in "Arria 10 SX Device Package Details" section.
  • Removed all references of the note about PCS-Direct support available in future release.
2013.12.02 Initial release.

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