Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

4.8. Resetting Transceiver Channels Revision History

Document Version Changes
  • Removed the step on deasserting pll_powerdown after tpll_powerdown in the Resetting the Transmitter During Device Operation section.
2020.05.08 Made the following change:
  • Updated pll_locked input hysteresis in reference to treq = 70 μs in the "General Options" table.
2018.06.15 Made the following changes:
  • Clarified the Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model instructions for when the CDR is in manual lock mode.
  • Updated the description for the "Enable RX channel reset control" parameter.
2017.11.06 Made the following change:
  • Added a note "If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel® recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block."
2016.05.02 Made the following changes
  • Added port "user reset" in "Typical Transceiver PHY Implementation" diagram.
  • Added note number 50.
  • Updated "Transceiver and Receiver Reset Sequence" diagram.
  • Added a note "Area in gray is don't care zone" in every diagram that has gray area in it.
  • Changes "tLTD" to "trx_digitalreset" in all the diagrams.
2015.12.18 Made the following changes:
  • Added description to the "Recommended Reset Sequence" section.
  • Added the "Arria 10 Default Settings Preset" fi