Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

4.8. Resetting Transceiver Channels Revision History

Document Version Changes
2021.06.10
  • Removed the step on deasserting pll_powerdown after tpll_powerdown in the Resetting the Transmitter During Device Operation section.
2020.05.08 Made the following change:
  • Updated pll_locked input hysteresis in reference to treq = 70 μs in the "General Options" table.
2018.06.15 Made the following changes:
  • Clarified the Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model instructions for when the CDR is in manual lock mode.
  • Updated the description for the "Enable RX channel reset control" parameter.
2017.11.06 Made the following change:
  • Added a note "If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel® recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block."
2016.05.02 Made the following changes
  • Added port "user reset" in "Typical Transceiver PHY Implementation" diagram.
  • Added note number 50.
  • Updated "Transceiver and Receiver Reset Sequence" diagram.
  • Added a note "Area in gray is don't care zone" in every diagram that has gray area in it.
  • Changes "tLTD" to "trx_digitalreset" in all the diagrams.
2015.12.18 Made the following changes:
  • Added description to the "Recommended Reset Sequence" section.
  • Added the "Arria 10 Default Settings Preset" figure.
  • Changed the signals and added a note in the "Typical Transceiver PHY Implementation" figure.
  • Added a parameter to the "General Options" table.
  • Updated the "Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure.
  • Updated the steps in the "Resetting the Transceiver in CDR Manual Lock Mode" section.
2015.11.02 Made the following changes:
  • Updated the "Reset Conditions" table.
  • Created the "Transceiver PHY Implementation" section.
  • Updated the "Typical Transceiver PHY Implementation" figure and moved it to the "Transceiver PHY Implementation" section.
  • Added the "Model 1: Default Model" and "Model 2: Acknowledgment Model" sections to the "How Do I Reset?" section.
  • Updated the "Transceiver PHY Reset Controller System Diagram" in the "Using the Transceiver PHY Reset Controller" section.
  • Added "Usage Examples for pll_select" to the "Transceiver PHY Reset Controller Interfaces" section.
2014.12.15 Made the following changes:
  • Updated the "Transmitter Reset Sequence After Power-Up" and "Transmitter Reset Sequence During Device Operation" figures.
  • Improved formatting in the "Transceiver PHY Reset Controller IP Core Top-Level Signals" figure.
  • Updated the description of the reset, tx_analogreset, and rx_analogreset parameters in the "Top-Level Signals" table.
2014.08.15 Made the following changes:
  • Updated the "Transmitter Reset Sequence After Power-Up" and "Receiver Reset Sequence Following Power-Up" figures.
  • Updated the "Resetting the Receiver During Device Operation" procedure and associated figure.
  • Updated the "Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode" figure.
2013.12.02 Initial release.

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