Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
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2.4.11. IP Core File Locations

When you generate your Transceiver Native PHY IP, the Quartus® Prime software generates the HDL files that define your instance of the IP. In addition, the Quartus Prime software generates an example Tcl script to compile and simulate your design in the ModelSim* simulator. It also generates simulation scripts for Synopsys* VCS, Aldec* Active-HDL, Aldec Riviera-Pro, and Cadence* Incisive Enterprise.

Figure 26. Directory Structure for Generated Files

The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.

Table 74.  Transceiver Native PHY Files and Directories
File Name Description
<project_dir> The top-level project directory.
<your_ip_name> .v or .vhd The top-level design file.