Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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3.11. Using PLLs and Clock Networks

In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process. You can specify the channel configuration and PLL usage.

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