Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.9.2.3. RX Bit Slip

To use the RX bit slip, select Enable rx_bitslip port and set the word aligner mode to bit slip. This adds rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time. When rx_bitslip is toggled, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at least two parallel clock cycles to allow synchronization. You can verify this feature by monitoring rx_parallel_data.

The RX bit slip feature is optional and may or may not be enabled.

Figure 137. RX Bit Slip in 8-bit Mode tx_parallel_data = 8'hbc


Figure 138. RX Bit Slip in 10-bit Mode tx_parallel_data = 10'h3bc


Figure 139. RX Bit Slip in 16-bit Mode tx_parallel_data = 16'hfcbc


Figure 140. RX Bit Slip in 20-bit Mode tx_parallel_data = 20'h3fcbc


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