Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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4.3.1.5. Dynamic Reconfiguration of Channel Using the Default Model

TX Channel

The numbers in this list correspond to the numbers in the following figure.

  1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while pll_cal_busy and tx_cal_busy are low.
  2. Perform dynamic reconfiguration after minimum 70 μs of asserting tx_analogreset.
  3. Deassert pll_powerdown after performing a dynamic reconfiguration.

    Deassert tx_analogreset. This step can be done at the same time or after you deassert pll_powerdown.

  4. The pll_locked signal goes high after the TX PLL acquires lock. Wait for minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked signal.
  5. Deassert tx_digitalreset after pll_locked goes high. The tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset duration after tx_analogreset is deasserted.
Figure 208. Dynamic Reconfiguration of Transmitter Channel During Device Operation

RX Channel

The numbers in this list correspond to the numbers in the following figure.

  1. Assert rx_analogreset and rx_digitalreset. Ensure that rx_cal_busy is low. You must reset the PCS by asserting rx_digitalreset every time you assert rx_analogreset.
  2. Perform dynamic reconfiguration after minimum 70 μs of asserting rx_analogreset.
  3. Deassert rx_analogreset after performing dynamic reconfiguration.
  4. The rx_is_lockedtodata signal goes high after the CDR acquires lock.
  5. Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before deasserting rx_digitalreset.
Figure 209. Dynamic Reconfiguration of Receiver Channel During Device Operation

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