Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Document Table of Contents Functional Description

The 1G/2.5G/5G/10G Multi-rate PHY Intel® FPGA IP core for Arria® 10 devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY). You can use the Native PHY IP core to configure the transceiver PHY for your protocol implementation.

Figure 80. Architecture of 2.5G, 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel® FPGA IP Parameter Editor.
The IP core includes the following interfaces:
  • Datapath client-interface:
    • 10GbE—XGMII, 64 bits
    • 1G/2.5GbE—GMII, 16 bit
    • 10M/100M/1