188.8.131.52. Functional Description
The 1G/2.5G/5G/10G Multi-rate PHY Intel® FPGA IP core for Intel® Arria® 10 devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY). You can use the Native PHY IP core to configure the transceiver PHY for your protocol implementation.
- Datapath client-interface:
- 10GbE—XGMII, 64 bits
- 1G/2.5GbE—GMII, 16 bit
- 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
For 1G/2.5/10G (MGBASE-T), select an interface based on the respective operating speed.
- Management interface— Avalon® memory-mapped interface host slave for PHY management.
- Datapath Ethernet interface with the following available options:
- 10GbE—Single 10.3125 Gbps serial link
- 2.5GbE—Single 3.125 Gbps serial link
- 1GbE—Single 1.25 Gbps SGMII serial link
- 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link
For 1G/2.5/10G (MGBASE-T), select an Ethernet interface based on the respective operating speed.
- Transceiver PHY dynamic reconfiguration interface—an Avalon® memory-mapped interface to read and write the Intel® Arria® 10 Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds.
- USXGMII—10M/100M/1G/2.5G/5G/10G speeds
- Full duplex data transmission
- USXGMII Auto-Negotiation
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