Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs

ATX PLL-to-ATX PLL Spacing Guidelines

For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart (skip 6).

For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GX channels, they must be placed 4 ATX PLLs apart (skip 3).

For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2).

For two ATX PLLs providing the serial clock for PCIe*/PIPE Gen3, they must be placed 4 ATX PLL apart (skip 3).

Note: If these spacing rules are violated, Intel® Quartus® Prime issues a critical warning.
When two ATX PLLs are being used, and you meet the following two conditions in your applications:
  • One of the ATX PLL re-calibration process is triggered.
  • The other channel (that is clocked by another ATX PLL) is in data transmission mode.
You must place the two ATX PLLs 7 ATX PLLs apart (skip 6). ATX PLLs between the 2 active ATX PLLs should not be used.

ATX PLL-to-fPLL Spacing Guidelines

If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:
  • When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.
  • ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/OC192/STM64, 10G GPON or protocol that has jitter integration start range <1MHz and data rate > 3Gbps.
The ATX PLL and fPLL must be separated at least by 1 ATX PLL in between.
If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:
  • fPLL user re-calibration process is triggered.
  • ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/OC192/STM64, 10G GPON or protocol that has jitter integration start range <1MHz and data rate > 3Gbps.
then the ATX PLL and fPLL must be separated at least by 1 ATX PLL in between (regardless of the ATX PLL and fPLL VCO frequency offset).

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