Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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6.16.1. Using PRBS Data Pattern Generator and Checker

Use the Arria® 10 PRBS generator and checker to simulate traffic and easily characterize high-speed links without fully implementing any upper protocol stack layer. The PRBS generator generates a self-aligning pattern and covers a known number of unique sequences. Because the PRBS pattern is generated by a Linear Feedback Shift Register (LFSR), the next pattern can be determined from the previous pattern. When the PRBS checker receives a portion of the received pattern, it can generate the next sequence of bits to verify whether the next data sequence received is correct.

The PRBS generator and checker are shared between the Standard and Enhanced datapaths through the PCS. Therefore, they have only one set of control signals and registers. The data lines from the various PCSs and shared PRBS generator are MUXed before they are sent to the PMA. When the PRBS generator is enabled, the data on the PRBS data lines is selected to be sent to the PMA. Either the data from the PCS or the data generated from the PRBS generator can be sent to the PMA at any time.

The PRBS generator and checker can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS generator and checker patterns can only be used when the PCS-PMA interface width is configured to 10 bits or 64 bits. For any other PCS-PMA width, to ensure the correct clocks are provided to the PRBS blocks you must first reconfigure the width to either 10 or 64 bits before using the PRBS generator and checker. For example, when the transceiver is configured to a 20-bit PCS/PMA interface, you must first reconfigure the PCS-PMA width to 10 bits before setting up the PRBS generator and checker. The PRBS setup does not automatically change the PCS/PMA width.

The 10-bit PCS-PMA width for PRBS9 is available for lower frequency testing. You can configure PRBS9 in either 10-bit or 64-bit width, based on the data rate. The FPGA fabric-PCS interface must run in the recommended speed range of the FPGA core. Therefore, you must configure PRBS9 in one of the two bit width modes, so that the FPGA fabric-PCS interface parallel clock runs in this operating range.

Examples:

  • If you want to use PRBS9 and the data rate is 2.5 Gbps, you can use the PRBS9 in 10-bit mode (PCS-PMA width = 10). In this case, the parallel clock frequency = Data rate / PCS-PMA width = 2500 Mbps/10 = 250 MHz.
  • If you want to use PRBS9 and the data rate is 6.4 Gbps, you can use the PRBS9 in 64-bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency = Data rate / PCS-PMA width = 6400 Mbps/64 = 100 MHz.
  • If you want to use PRBS9 and the data rate is 12.5 Gbps, you can use the PRBS9 in 64 bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency = Data rate / PCS-PMA width = 12500 Mbps/64 = 195.3125 MHz.
Table 291.   PRBS Supported Polynomials and Data WidthsUse the 10-bit mode of PRBS9 when the data rate is lower than 3 Gbps.
Pattern Polynomial 64-Bit 10-Bit
PRBS7 G(x) = 1+ x6 + x7 X  
PRBS9 G(x) = 1+ x5 + x9 X X
PRBS15 G(x) = 1+ x14 + x15 X
PRBS23 G(x) = 1+ x18 + x23 X
PRBS31 G(x) = 1+ x28 + x31 X

The PRBS checker has the following control and status signals available to the FPGA fabric:

  • rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr.
  • rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
  • rx_prbs_err_clr—Used to reset the rx_prbs_err signal.

Enable the PRBS checker control and status ports through the Native PHY IP Parameter Editor in the Quartus Prime software.

Use the PRBS soft accumulators to count the number of accumulated bits and errors when the hard PRBS blocks are used. For more information about using the accumulators and reading the error values, refer to the PRBS Soft Accumulators section.

Table 292.   Register Map for PRBS Generators for bonded and non bonded designs
Reconfiguration Address (HEX) Reconfiguration Bit Attribute Name Related Addresses Attribute Encoding Bit Encoding Description
0x006 [2:0] tx_pma_data_sel 0x8 prbs_pat 3'b100 Select PRBS Generator Block
[3] prbs9_dwidth prbs9_10b 1'b1 Enable PRBS9 in 10-bit mode
prbs9_64b 1'b0 Enable PRBS9 in 64-bit mode
[6] prbs_clken prbs_clk_dis 1'b0 Disable PRBS generator clock
prbs_clk_en 1'b1 Enable PRBS generator clock
0x007 [7:4] prbs_gen_pat 0x8 prbs_7 4'b0001 Enable PRBS7 pattern
prbs_9 4'b0010 Enable PRBS9 pattern
prbs_15 4'b0100 Enable PRBS15 pattern
prbs_23 4'b1000 Enable PRBS23 pattern
prbs_31 4'b0000 Enable PRBS31 pattern
0x008 [4] prbs_gen_pat 0x7 prbs_7 1'b0 Enable PRBS7 pattern
prbs_9 1'b0 Enable PRBS9 pattern
prbs_15 1'b0 Enable PRBS15 pattern
prbs_23 1'b0 Enable PRBS23 pattern
prbs_31 1'b1 Enable PRBS31 pattern
[6:5] tx_pma_data_sel 0x6 prbs_pat 2'b00 Enable PRBS generator
0x110 [2:0] ser_mode sixty_four_bit 3'b011 64-bit mode
ten_bit 3'b100 10-bit mode
0x111 [4:0] x1_clock_source_sel 0x119 xn_non_bonding64 5'b11000 Enables xn non bonding
Table 293.  Register Map for PRBS Checker for bonded and non bonded designs
Reconfiguration Address (HEX) Reconfiguration Bit Attribute Name Related Addresses Attribute Encoding Bit Encoding Description
0x00A [7] prbs_clken   prbs_clk_dis 1'b0 Disable PRBS checker clock
prbs_clk_en 1'b1 Enable PRBS checker clock
0x00B [3:2] rx_prbs_mask prbsmask1024 2'b11 Counter threshold to 1023
prbsmask128 2'b00 Counter threshold to 127
prbsmask256 2'b01 Counter threshold to 255
prbsmask512 2'b10 Counter threshold to 511
[7:4] prbs_ver 0xC prbs_7 4'b0001 Enable PRBS7 pattern
prbs_9 4'b0010 Enable PRBS9 pattern
prbs_15 4'b0100 Enable PRBS15 pattern
prbs_23 4'b1000 Enable PRBS23 pattern
prbs_31 4'b0000 Enable PRBS31 pattern
0x00C [0] prbs_ver 0xB prbs_7 1'b0 Enable PRBS7 pattern
prbs_9 1'b0 Enable PRBS9 pattern
prbs_15 1'b0 Enable PRBS15 pattern
prbs_23 1'b0 Enable PRBS23 pattern
prbs_31 1'b1 Enable PRBS31 pattern
[3] prbs9_dwidth   prbs9_10b 1'b1 PRBS9 10-bit
prbs9_64b 1'b0 PRBS9 64-bit
0x13F [3:0] deser_factor   10 4'b0001 10-bit mode
64 4'b1110 64-bit mode
64 You must read and save the value in the register 0x111[5:0] before changing the x1_clcok_source_sel setting to xN non bonding. To disable the PRBS generator, write the original values back into the read-modify-write address.

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