Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.9.3.1. Transceiver PHY IP

Arria 10 GT transceiver channels are implemented using the Native PHY IP with the Basic (Enhanced PCS) transceiver configuration rule.

  • To support 25.8 Gbps, the Enhanced PCS must be configured in basic mode with the low latency check box unselected. To configure the Enhanced PCS, do not enable any functional blocks in the Enhanced PCS (that is, disable Block Synchronizer, Gearbox, Scrambler, and Encoder).
  • You can also use the PCS-Direct mode for 25.8 Gbps.

You can bundle several GT transceiver channels with one Native PHY IP instantiation, but you must instantiate a separate ATX PLL IP for every ATX PLL used.

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