Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

6.6. Arbitration

Figure 272.  Arria® 10 ATX PLL with Embedded Streamer
Figure 273.  Arria® 10 Native PHY with Embedded Streamer

In Arria® 10 devices, there are two levels of arbitration:

  • Reconfiguration interface arbitration with the PreSICE calibration engine

    When you have control over the internal configuration bus, refer to the second level of arbitration: Arbitration between multiple masters within the Native PHY/PLL IPs.

    For more details about arbitration between the reconfiguration interface and PreSICE, refer to the Calibration chapter.

  • Arbitration between multiple masters within the Native PHY/PLL IPs

    Below are the feature blocks that can access the programmable registers:

    • Embedded reconfiguration streamer (Available in the Native PHY and ATX PLL IPs only)
    • NPDME
    • User reconfiguration logic connected to the reconfiguration interface

    When the