Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.1.5. Receiver Buffer

The receiver input buffer receives serial data from rx_serial_data and feeds the serial data to the clock data recovery (CDR) unit and deserializer. Select High Speed Differential I/O, CML, Differential LVPECL, and LVDS for the I/O standard of the Intel® Arria® 10 receiver pin in Intel® Quartus® Prime Assignment Editor or QSF file. CML, Differential LVPECL, and LVDS are only used on AC coupled links.

Figure 228. Receiver Buffer


The receiver buffer supports the following features:

  • Programmable common mode voltage (VCM)
  • Programmable differential On-Chip Termination (OCT)
  • Signal Detector
  • Continuous Time Linear Equalization (CTLE)
  • Variable Gain Amplifiers (VGA)
  • Adaptive Parametric Tuning Engine
  • Decision Feedback Equalization (DFE)

Did you find the information on this page useful?

Characters remaining:

Feedback Message