Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

6.5. Embedded Reconfiguration Streamer

You can optionally enable the embedded reconfiguration streamer in the Native PHY IP core, ATX PLL IP core, or both to automate the reconfiguration operation.

The embedded reconfiguration streamer is a feature block that can perform Avalon® memory-mapped interface transactions to access channel/ATX PLL configuration registers in the transceiver.

When you enable the embedded streamer, the Native PHY/ATX PLL IP cores embed the reconfiguration profiles and reconfiguration control logic in the IP files.

For the ATX PLL IP, you can control the embedded streamer block through the reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PLL’s soft control and status registers.

Table 265.  Control and Status Register Memory Map for Embedded Reconfiguration Streamer in ATX PLL IP
Reconfiguration Address (hex) Reconfiguration Bit Attribute Name Attribute Description Bit Encoding Transceiver Block Description
340 7 cfg_load Start streaming 1'b1 Embedded Reconfiguration Streamer Set to 1'b1 to initiate streaming, self-clearing bit
[2:0] cfg_sel Configuration profile select Direct mapped