6.5. Embedded Reconfiguration Streamer
The embedded reconfiguration streamer is a feature block that can perform Avalon® memory-mapped interface transactions to access channel/ATX PLL configuration registers in the transceiver.
When you enable the embedded streamer, the Native PHY/ATX PLL IP cores embed the reconfiguration profiles and reconfiguration control logic in the IP files.
For the ATX PLL IP, you can control the embedded streamer block through the reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PLL’s soft control and status registers.
|Reconfiguration Address (hex)||Reconfiguration Bit||Attribute Name||Attribute Description||Bit Encoding||Transceiver Block||Description|
|340||7||cfg_load||Start streaming||1'b1||Embedded Reconfiguration Streamer||Set to 1'b1 to initiate streaming, self-clearing bit|
|[2:0]||cfg_sel||Configuration profile select||Direct mapped|