Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.5.2.2.1. TX FIFO Soft Bonding

The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable) by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull, tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted high, the frame generator reads data from the TX FIFO.

A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding. The following figure shows the state of the pre-fill process.

Figure 33. TX Soft Bonding Flow

The following figure shows that after deasserting tx_digitalreset, TX soft bonding logic starts filling the TX FIFO until all lanes are full.

Figure 34. TX FIFO Pre-fill (6-lane Interface)

After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat the TX FIFO pre-fill stage.

For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You can begin sending an Interlaken word to the TX FIFO after tx_digitalreset deasserts.

The following figure shows the MAC layer sending valid data to the Native PHY after the pre-fill stage. tx_enh_frame_burst_en is asserted, allowing the frame generator to read data from the TX FIFO. The TX MAC layer can now control tx_enh_data_valid and write data to the TX FIFO based on the FIFO status signals.

Figure 35. MAC Sending Valid Data (6-lane Interface)

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