Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.10. Standard PCS Ports

Figure 25. Transceiver Channel using the Standard PCS PortsStandard PCS ports appear if either one of the transceiver configuration modes is selected that uses Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of those that uses Standard PCS.

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <w>—The width of the interface
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 67.  TX Standard PCS: Data, Control, and Clocks
Name Direction Clock Domain Description
tx_parallel_data[<n>128-1:0]

Input

tx_clkout

TX parallel data input from the FPGA fabric to the TX PCS.

unused_tx_parallel_data

Input

tx_clkout This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of tx_parallel_data. Connect all these bits to 0. If you do not connect the unused data bits to 0, then TX parallel data may not be serialized correctly by the Native PHY IP core.
tx_coreclkin[<n>-1:0] Input Clock

The FPGA fabric clock. This clock drives the write port of the TX FIFO.

tx_clkout[<n>-1:0]

Output

Clock

This is the parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configuration. This clocks the tx_parallel_data from the FPGA fabric to the TX PCS.

Table 68.  RX Standard PCS: Data, Control, Status, and Clocks
Name Direction Clock Domain Description
rx_parallel_data[<n> 128-1:0]

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

RX parallel data from the RX PCS to the FPGA fabric. For each 128-bit word of rx_parallel_data, the data bits correspond to rx_parallel_data[7:0] when 8B/10B decoder is enabled and rx_parallel_data[9:0] when 8B/10B decoder is disabled.

unused_rx_parallel_data

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_parallel_data. These outputs can be left floating.
rx_clkout[<n>-1:0]

Output

Clock

The low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX Standard PCS.

rx_coreclkin[<n>-1:0] Input Clock

RX parallel clock that drives the read side clock of the RX FIFO.

Table 69.  Standard PCS FIFO
Name Direction Clock Domain Description
tx_std_pcfifo_full[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Indicates when the standard TX FIFO is full.

tx_std_pcfifo_empty[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Indicates when the standard TX FIFO is empty.

rx_std_pcfifo_full[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

Indicates when the standard RX FIFO is full.

rx_std_pcfifo_empty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

Indicates when the standard RX FIFO is empty.

Table 70.  Rate Match FIFO
Name Direction Clock Domain Description
rx_std_rmfifo_full[<n>-1:0]

Output

Asynchronous

Rate match FIFO full flag. When asserted the rate match FIFO is full. You must synchronize this signal. This port is only used for GigE mode.

rx_std_rmfifo_empty[<n>-1:0]

Output

Asynchronous

Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode.

rx_rmfifostatus[<n>-1:0]

Output

Asynchronous

Indicates FIFO status. The following encodings are defined:

  • 2'b00: Normal operation
  • 2'b01: Deletion, rx_std_rmfifo_full = 1
  • 2'b10: Insertion, rx_std_rmfifo_empty = 1
  • 2'b11: Full. rx_rmfifostatus is a part of rx_parallel_data. rx_rmfifostatus corresponds to rx_parallel_data[14:13].
Table 71.  8B/10B Encoder and Decoder
Name Direction Clock Domain Description
tx_datak

Input

tx_clkout

tx_datak is exposed if 8B/10B enabled and simplified data interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of tx_parallel_data is data. tx_datak is a part of tx_parallel_data when simplified data interface is not set.
tx_forcedisp[<n>(<w>/<s>-1:0]

Input

Asynchronous

This signal allows you to force the disparity of the 8B/10B encoder. When "1", forces the disparity of the output data to the value driven on tx_dispval. When "0", the current running disparity continues. tx_forcedisp is a part of tx_parallel_data. tx_forcedisp corresponds to tx_parallel_data[9].

tx_dispval[<n>(<w>/<s>-1:0]

Input

Asynchronous

Specifies the disparity of the data. When 0, indicates positive disparity, and when 1, indicates negative disparity. tx_dispval is a part of tx_parallel_data. tx_dispval corresponds to tx_dispval[10].

rx_datak[<n><w>/<s>-1:0]

Output

rx_clkout

rx_datak is exposed if 8B/10B is enabled and simplified data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of rx_parallel_data is data. rx_datak is a part of rx_parallel_data when simplified data interface is not set.

rx_errdetect[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When asserted, indicates a code group violation detected on the received code group. Used along with rx_disperr signal to differentiate between code group violation and disparity errors. The following encodings are defined for rx_errdetect/rx_disperr:

  • 2'b00: no error
  • 2'b10: code group violation
  • 2'b11: disparity error. rx_errdetect is a part of rx_parallel_data. For each 128-bit word, rx_errdetect corresponds to rx_parallel_data[9].
rx_disperr[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When asserted, indicates a disparity error on the received code group. rx_disperr is a part of rx_parallel_data. For each 128-bit word, rx_disperr corresponds to rx_parallel_data[11].
rx_runningdisp[<n><w>/<s>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

When high, indicates that rx_parallel_data was received with negative disparity. When low, indicates that rx_parallel_data was received with positive disparity. rx_runningdisp is a part of rx_parallel_data. For each 128 bit word, rx_runningdisp corresponds to rx_parallel_data[15].
rx_patterndetect[<n><w>/<s>-1:0] Output Asynchronous When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary. rx_patterndetect is a part of rx_parallel_data. For each 128-bit word, rx_patterndetect corresponds to rx_parallel_data[12].
rx_syncstatus[<n><w>/<s>-1:0] Output Asynchronous When asserted, indicates that the conditions required for synchronization are being met. rx_syncstatus is a part of rx_parallel_data. For each 128-bit word, rx_syncstatus corresponds to rx_parallel_data[10].
Table 72.  Word Aligner and Bitslip
Name Direction Clock Domain Description
tx_std_bitslipboundarysel[5 <n>-1:0] Input

Asynchronous

Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip.

rx_std_bitslipboundarysel[5 <n>-1:0] Output

Asynchronous

This port is used in deterministic latency word aligner mode. This port reports the number of bits that the RX block slipped. This port values should be taken into consideration in either Deterministic Latency Mode or Manual Mode of Word Aligner.

rx_std_wa_patternalign[<n>-1:0] Input

Synchronous to rx_clkout

Active when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_std_wa_patternalign. When the PCS-PMA Interface width is 10 bits, rx_std_wa_patternalign is level sensitive. For all the other PCS-PMA Interface widths, rx_std_wa_patternalign is positive edge sensitive.

You can use this port only when the word aligner is configured in manual or deterministic latency mode.

When the word aligner is in manual mode, and the PCS-PMA interface width is 10 bits, this is a level sensitive signal. In this case, the word aligner monitors the input data for the word alignment pattern, and updates the word boundary when it finds the alignment pattern.

For all other PCS-PMA interface widths, this signal is edge sensitive.This signal is internally synchronized inside the PCS using the PCS parallel clock and should be asserted for at least 2 clock cycles to allow synchronization.

rx_std_wa_a1a2size[<n>-1:0] Input

Asynchronous

Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits.

rx_bitslip[<n>-1:0] Input

Asynchronous

Used when word aligner mode is bitslip mode. When the Word Aligner is in either Manual (PLD controlled), Synchronous State Machine or Deterministic Latency ,the rx_bitslip signal is not valid and should be tied to 0. For every rising edge of the rx_std_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data.

Table 73.  Bit Reversal and Polarity Inversion
Name Direction Clock Domain Description
rx_std_byterev_ena[<n>-1:0]

Input

Asynchronous

This control signal is available when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface. Used if the MSB and LSB of the transmitted data are erroneously swapped.

rx_std_bitrev_ena[<n>-1:0]

Input

Asynchronous

When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.

tx_polinv[<n>-1:0]

Input

Asynchronous

When asserted, the TX polarity bit is inverted. Only active when TX bit polarity inversion is enabled.

rx_polinv[<n>-1:0]

Input

Asynchronous

When asserted, the RX polarity bit is inverted. Only active when RX bit polarity inversion is enabled.

rx_std_signaldetect[<n>-1:0]

Output

Asynchronous

When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime Settings File (.qsf) assignment. This signal is required for the PCI Express*, SATA and SAS protocols.

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