Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

2.4.10. Standard PCS Ports

Figure 25. Transceiver Channel using the Standard PCS PortsStandard PCS ports appear if either one of the transceiver configuration modes is selected that uses Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of those that uses Standard PCS.

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <w>—The width of the interface
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 67.  TX Standard PCS: Data, Control, and Clocks
Name Direction Clock Domain Description



TX parallel data input from the FPGA fabric to the TX PCS.