Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.1.3. Transmitter Buffer

The transmitter buffer includes the following circuitry:

  • High Speed Differential I/O
  • Programmable differential output voltage (VOD)
    • Main tap
  • Programmable four-tap pre-emphasis circuitry
    • Two pre-cursor taps
    • Two post-cursor taps
  • Power distribution network (PDN) induced inter-symbol interference (ISI) compensation
  • Internal termination circuitry
  • Receiver detect capability to support PCI Express* and Quick Path Interconnect (QPI) configurations
Figure 225. Transmitter Buffer


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