Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
Give Feedback CDR and CMU Reference Clock Switching

You can use the reconfiguration interface to specify which reference clock source drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five different reference clock sources.

Before initiating a reference clock switch, ensure that your CDR and CMU defines more than one reference clock source. For the CDR, specify the parameter on the RX PMA tab during the Native PHY IP parameterization. For the CMU, specify the Number of PLL reference clocks under the PLL tab when parameterizing the CMU PLL.

The following table describes the addresses and bits for switching CDR and CMU reference clock inputs. The number of exposed rx_cdr_refclk (CDR) or pll_refclk (CMU) varies according to the number of reference clocks you specify. Use the CMU reconfiguration interface for switching the CMU reference clock.

Table 271.  Register Map for Switching CDR Reference Clock Inputs
Native PHY Port Description Address Bits
cdr_refclk0 Represents logical refclk0. Lookup register