Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents CDR and CMU Reference Clock Switching

You can use the reconfiguration interface to specify which reference clock source drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five different reference clock sources.

Before initiating a reference clock switch, ensure that your CDR and CMU defines more than one reference clock source. For the CDR, specify the parameter on the RX PMA tab during the Native PHY IP parameterization. For the CMU, specify the Number of PLL reference clocks under the PLL tab when parameterizing the CMU PLL.

The following table describes the addresses and bits for switching CDR and CMU reference clock inputs. The number of exposed rx_cdr_refclk (CDR) or pll_refclk (CMU) varies according to the number of reference clocks you specify. Use the CMU reconfiguration interface for switching the CMU reference clock.

Table 271.  Register Map for Switching CDR Reference Clock Inputs
Native PHY Port Description Address Bits
cdr_refclk0 Represents logical refclk0. Lookup register x16A[7:0] stores the mapping from logical refclk0 to the physical refclk. 0x16A (Lookup Register) [7:0]
cdr_refclk1 Represents logical refclk1. Lookup register x16B[7:0] stores the mapping from logical refclk1 to the physical refclk. 0x16B (Lookup Register) [7:0]
cdr_refclk2 Represents logical refclk2. Lookup register x16C[7:0] stores the mapping from logical refclk2 to the physical refclk. 0x16C (Lookup Register) [7:0]
cdr_refclk3 Represents logical refclk3. Lookup register x16D[7:0] stores the mapping from logical refclk3 to the physical refclk. 0x16D (Lookup Register) [7:0]
cdr_refclk4 Represents logical refclk4. Lookup register x16E[7:0] stores the mapping from logical refclk4 to the physical refclk. 0x16E (Lookup Register) [7:0]
N/A CDR refclk selection MUX. 0x141 [7:0]

When performing a reference clock switch, note the logical reference clock to switch to and the respective address and bits. After determining the logical reference clock, follow this procedure to switch to the selected CDR reference clock:

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Read from the lookup register and save the required 8-bit pattern. For example, switching to logical refclk3 requires saving bits[7:0] at address 0x16D.
  3. Perform a read-modify-write to bits [7:0] at address 0x141 using the 8-bit value obtained from the lookup register.
  4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.

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