Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.6.9.1. SDR XGMII TX Interface

Table 173.  SDR TX XGMII Interface
Signal Name Direction Description
xgmii_tx_dc[71:0]

Input

Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control. Synchronous to mgmt_clk.

  • Lane 0–[7:0]/[8], [43:36]/[44]
  • Lane 1–[16:9]/[17], [52:45]/[53]
  • Lane 2–[25:18]/[26], [61:54]/[62]
  • Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_tx_clk

Input

The XGMII SDR TX clock which runs at 156.25 MHz.

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