Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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6.8. Steps to Perform Dynamic Reconfiguration

You can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfiguration interface.

The following procedure shows the steps required to reconfigure the channel and PLL blocks.

  1. Enable dynamic reconfiguration in the IP.
  2. Enable the desired configuration file formats in the IP.
  3. Enable the desired dynamic reconfiguration features (such as multiple reconfiguration profiles, including PMA analog settings in configuration files) or feature blocks (such as embedded reconfiguration streamer and NPDME).
  4. If you are using:
    • Direct reconfiguration flow—Refer to the register map for feature address and valid value of write data for the feature.
    • IP guided reconfiguration flow—Note the settings of the base configuration and generate the corresponding configuration files. Note the settings of the modified configuration and generate the corresponding configuration files. Find out the differences in settings between the base and modified configurations.
    • IP guided reconfiguration flow using multiple profiles—Create and store the parameter settings between the various configurations or profiles using configuration files. Find out the differences in settings between the various configurations or profiles using configuration files.
    • IP guided reconfiguration flow using the embedded streamer—Refer to the control and status register map of the embedded reconfiguration streamer to stream the desired profile settings.
    • Reconfiguration flow for special cases—Refer to the lookup registers to be accessed for each special case, such as TX PLL switching, TX PLL reference clock switching, and RX CDR reference clock switching.
  5. Place the channels in digital reset either simultaneously or one after another. For details about placing the channel in reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.

    If you are reconfiguring:

    • PLLs—Place the channel transmitter associated with the PLL in reset (digital).
    • TX simplex channels—Place the TX channels being reconfigured in reset (digital).
    • RX simplex channels—Place the RX channels being reconfigured in reset (digital).
    • Duplex channels—Place the channel TX and RX being reconfigured in reset (digital).
  6. If you are reconfiguring across data rates or protocol modes or enabling/disabling PRBS, place the channels in analog reset. For details about placing the channel in analog reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.

    If you are reconfiguring:

    • PLLs—Place the channel transmitter associated with the PLL in reset (analog).
    • TX simplex channels—Place the TX channels being reconfigured in reset (analog).
    • RX simplex channels—Place the RX channels being reconfigured in reset (analog).
    • Duplex channels—Place the channel TX and RX being reconfigured in reset (analog).
  7. Check for internal configuration bus arbitration. If PreSICE has control, request bus arbitration, otherwise go to the next step. For more details, refer to the "Arbitration" section.
  8. Perform the necessary reconfiguration using the flow described in the following sections:
    • Direct Reconfiguration Flow
    • Native PHY or PLL IP Guided Reconfiguration Flow
    • Reconfiguration Flow for Special Cases
  9. Perform all necessary reconfiguration. If reconfiguration involved data rate or protocol mode changes, then you may have to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA Analog Parameters section for more details.
  10. If reconfiguration involved data rate or protocol mode change, then request recalibration and wait for the calibration to complete. Calibration is complete when *_cal_busy is deasserted. For more details about calibration registers and the steps to perform recalibration, refer to the Calibration chapter.

    If you reconfigured:

    • PLL for data rate change—you must recalibrate the PLL and the channel TX.
    • TX simplex channel for data rate change—you must recalibrate the channel TX.
    • RX simplex channel for data rate change—you must recalibrate the channel RX.
    • Duplex channel for data rate change—you must recalibrate the channel TX and RX.
  11. Release the channel analog resets. For details about placing the channel in reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.

    If you reconfigured:

    • PLLs—Release the reset (analog) of the channel transmitters associated with the PLL reconfigured.
    • TX simplex channels—Release the reset (analog) of the TX channels reconfigured.
    • RX simplex channels—Release the reset (analog) of the RX channels reconfigured.
    • Duplex channels—Release the reset (analog) of the TX and RX channels reconfigured.
  12. Release the channel digital resets either simultaneously or one after another. For details about releasing the channel resets, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter. (The figures in these sections are for analog resets, but they also contain timing information about digital resets.)

    If you reconfigured:

    • PLLs—Release the reset (digital) of the channel transmitters associated with the PLL reconfigured.
    • TX simplex channels—Release the reset (digital) of the TX channels reconfigured.
    • RX simplex channels—Release the reset (digital) of the RX channels reconfigured.
    • Duplex channels—Release the reset (digital) of the TX and RX channels reconfigured.
Note: You cannot merge multiple reconfiguration interfaces across multiple IP blocks (merging independent instances of simplex TX/RX into the same physical location or merging separate CMU PLL and TX channel into the same physical location) when you use the optional reconfiguration logic soft control registers.

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