Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI

The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process. It automatically synchronizes and aligns the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment pattern (K28.5).
Figure 116.  Deterministic Latency State Machine in the Word Aligner


When using deterministic latency state machine mode, assert rx_std_wa_patternalign to initiate the pattern alignment after the reset sequence is complete. This is an edge-triggered signal in all cases except one: when the word aligner is in manual mode and the PMA width is 10, in which case rx_std_wa_patternalign is level sensitive.

Figure 117. Word Aligner in Deterministic Mode Waveform

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