Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.3.5.1. Clock and Reset Interfaces

Table 113.  Clock and Reset Signals
Signal Name Direction Description
tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g Input High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625 MHz.
rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock. This clock frequency can be 644.53125 MHz or 322.2656 MHz.
rx_cdr_ref_clk_1g Input 1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock is only required if 1G is enabled.
tx_pma_clkout Output Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is 161.13 MHz for 10G with FEC enabled.
rx_pma_clkout Output Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is 161.13 MHz for 10G with FEC enabled.
tx_clkout Output