Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.3.5.1. Clock and Reset Interfaces

Table 113.  Clock and Reset Signals
Signal Name Direction Description
tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g Input High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625 MHz.
rx_cdr_ref_clk_10g Input 10G PHY RX PLL reference clock. This clock frequency can be 644.53125 MHz or 322.2656 MHz.
rx_cdr_ref_clk_1g Input 1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock is only required if 1G is enabled.
tx_pma_clkout Output Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is 161.13 MHz for 10G with FEC enabled.
rx_pma_clkout Output Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is 161.13 MHz for 10G with FEC enabled.
tx_clkout Output XGMII/GMII TX clock for the TX parallel data source interface. This clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with FEC enabled.
rx_clkout Output XGMII RX clock for the RX parallel data source interface. This clock frequency is 257.81 in 10G mode, and 161.13 MHz with FEC enabled.
tx_pma_div_clkout Output The divided 33 clock from the TX serializer. You can use this clock for the for xgmii_tx_clk or xgmii_rx_clk. The frequency is 156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC.
rx_pma_div_clkout Output The divided 33 clock from CDR recovered clock. The frequency is 156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC. This clock is not used for clocking the 10G RX datapath.
tx_analogreset Input Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk.
tx_digitalreset Input Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_analogreset Input Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk.
rx_digitalreset Input Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk.
usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk.

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