Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

7.4. User Recalibration

User Recalibration is needed if below conditions are met:
  • During Device Power Up:
    • During device power up, CLKUSR is asserted and running, but the transceiver reference clock remains deasserted until after the power up process is complete.
    • During device power up, CLKUSR and the transceiver reference clock are asserted and running. When the device power up process is complete, the transceiver reference clock changes frequency. Either the transceiver reference clock could become unstable, or your application requires a different transceiver reference clock during normal operation, which could cause a data rate change.
  • After a dynamic reconfiguration process that triggers a data rate change:

    After device power up in normal operation, you reconfigure the transceiver data rate by changing the channel configurations or the PLLs, recalibrate the:

    • ATX PLL if ATX PLL has new VCO frequency to support new data rate.
    • fPLL if the fPLL has new VCO frequency to support new data rate.
      Note: fPLL recalibration is not needed if the dynamic reconfiguration method used to achieve new data rate (new VCO frequency) is done using the fPLL L counter /1,2,4,8 division factor.
    • CDU/CMU as TX PLL. You must recalibrate the RX PMA of the channel which uses the CMU as TX PLL.
    • RX PMA and TX PMA channel if the transceiver configuration changes to support new data rates.
  • Other conditions that require a user recalibration:
    • Recalibrate the fPLL if the fPLL is connected as a second PLL (downstream cascaded PLL). The downstream fPLL received the reference clock from the upstream PLL (could be from fPLL/ CDR). Recalibrating the second fPLL is important especially if the upstream PLL output clock (which is the downstream fPLL's reference clock) is not present or stable during power-up calibration.
    • For ATX PLL or fPLL used to drive PLL feedback compensation bonding, recalibrate the PLL after power up calibration.
Note: If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.

You can initiate the recalibration process by writing to the specific recalibration registers. You must also reset the transceivers after performing user recalibration. For example, if you perform data rate auto-negotiation that involves PLL reconfiguration, and PLL and channel interface switching, then you must reset the transceivers.

The proper reset sequence is required after calibration. Intel recommends you use the Transceiver PHY Reset Controller which has tx_cal_busy and rx_cal_busy inputs and follow Intel's recommended reset sequence. You need to connect tx_cal_busy and rx_cal_busy from the Native PHY IP core outputs to the reset controller inputs in your design. Reset upon calibration is automatically processed when you perform user recalibration.

Follow these steps to perform user recalibration:

  1. Request internal configuration bus user access to the calibration registers by writing 0x2 to offset address 0x0[7:0].
  2. Wait for reconfig_waitrequest to be deasserted (logic low). Or wait until capability register of PreSICE Avalon® memory-mapped interface control =0x0. The avmm_busy status register is 0x281[2] for PMA channel calibration and 0x280[2] for ATX PLL and fPLL calibration.
  3. Set the required calibration enable bits by doing Read-Modify-Write the proper value to offset address 0x100. You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to ensure adaptation triggering is disabled.
  4. Set rate switch flag register for PMA calibration, skip this step for ATX PLL and fPLL calibration.
    • Read-Modify-Write 0x1 to offset address 0x166[7] if no CDR rate switch.
    • Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with different CDR bandwidth setting.
  5. Set the proper value to capability register 0x281[5:4] for PMA calibration to enable/disable tx_cal_busy or rx_cal_busy output.
    • To enable rx_cal_busy, Read-Modify-Write 0x1 to 0x281[5].
    • To disable rx_cal_busy, Read-Modify-Write 0x0 to 0x281[5].
    • To enable tx_cal_busy, Read-Modify-Write 0x1 to 0x281[4].
    • To disable tx_cal_busy, Read-Modify-Write 0x0 to 0x281[4].
  6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]. Recalibration is in progress until the cal_busy signals are deasserted (logic low).
  7. Periodically check the *cal_busy output signals or read the capability registers to check *cal_busy status until calibration is complete.

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