Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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Document Table of Contents

Table 252.  Summary of Receiver Equalization Modes
Receiver Equalization Modes
CTLE adaptation mode Manual, Triggered (use the triggered mode for PCIe* Gen3 only)
DFE adaptation mode Adaptation enabled, Manual, Disabled
Number of fixed DFE taps 3, 7, 11
Follow these steps to trigger DFE adaptation:
  1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].
  2. Monitor and wait for avmm_waitrequest to be deasserted (logic low) if "Separate reconfig_waitrequest from PreCISE" option is disabled. Otherwise, monitor and wait for register bit 0x281 bit[2] to go low if "Separate reconfig_waitrequest from PreCISE" and "Enable control and status registers" option is enabled.
  3. Select adaptation control by Read-Modify-Write 0x1 to bit[4] of address 0x149.
  4. Enable adaptation trigger by Read-Modify-Write 0x1 to bit[6] of address 0x100.
  5. Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0].
  6. Repeat step 2.
  7. Monitor DFE adaptation completion by checking register bit 0x100 bit[6] to go low. This confirms DFE trigger adaptation routine is complete.

Configuration Methods

Configure the modes using one of the following methods:

Method 1 - Using Arria 10 Transceiver Native PHY IP Core

  1. Select the CTLE/DFE mode in the RX PMA tab of the PHY IP Core
  2. Compile the design
  3. Choose one the following:
    • If CTLE or DFE is in Manual mode, set the CTLE gain value or DFE taps using one of the following ways:
      1. Assignment Editor/.qsf- Recompile the design to make these values effective.

        Refer to Analog Parameter Settings for more details about Receiver Equalization Settings.

      2. Avalon® memory-mapped interface - Value written through Avalon® memory-mapped interface take precedence over values defined in Assignment Editor. Use this method to dynamically set values and hence avoid re-compilation.

        Refer to Arria 10 Transceiver Register Map for more details on Avalon® memory-mapped interface and to perform dynamic read/write.

Method 2 - Using Avalon® Memory-Mapped Interface

  1. Any changes you make using Avalon® memory-mapped interface take precedence over what was configured in Native PHY IP GUI and/or Assignment Editor.
    1. For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using the reconfiguration interface. The values are written dynamically and do not require design re-compilation.

      Refer to Arria 10 Register Map for details on the specific registers that set the CTLE gain values/DFE taps.

    2. For dynamically changing DFE and CTLE Adaptation modes, refer to CTLE Settings in Triggered Adaptation Mode, Arria 10 Register Map and Arria 10 DFE Adaptation Tool for the list of adaptation registers. Use the reconfiguration interface to change the register settings.
    Note: You must set VGA manually for all combinations of CTLE mode and DFE modes.

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