Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.7.2. Hard Transceiver PHY Registers

Table 145.  Hard Transceiver PHY Registers
Addr Bit Access Name Description
0x000-0x3FF [9:0] RW Access to HSSI registers All registers in the physical coding sub-layer (PCS) and physical media attachment (PMA) that you can dynamically reconfigure are in this address space. Refer to the Arria 10 Dynamic Transceiver Reconfiguration chapter for further information.

Did you find the information on this page useful?

Characters remaining:

Feedback Message