Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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6.12.3. CTLE Settings in Triggered Adaptation Mode

CTLE triggered adaptation mode should only be used for PCIe* Gen3. Refer to the section "How to enable CTLE and DFE" in Chapter Arria® 10 Transceiver PHY Architecture of Arria 10 Transceiver PHY User Guide for details on using the triggered adaptation mode of CTLE.

User need to change the register bit settings accordingly when moving from PCIe Gen1/2 (CTLE manual, DFE disabled) to PCIe Gen3 (CTLE triggered, DFE disabled) or vice versa. Refer to Register Map for CTLE triggered and CTLE manual settings for the difference in register bit settings when moving from CTLE manual, DFE disabled to CTLE triggered, DFE disabled. User need to perform read modify writes to all the register bits that differ through dynamic reconfiguration Avalon® memory-mapped interface.

Table 276.  Register Map for CTLE triggered and CTLE manual settings
Register Address Register Bit Description Value
CTLE Triggered, DFE Disabled CTLE Manual, DFE Disabled
0x123 1:1 Enable Adaptation Slicers 1'b1 1'b0
2:2 Enable DFE Fix Tap 8 to 11 1'b0
3:3 Enable DFE Fix Tap 4 to 7 1'b0
0x148 0:0 Enable DFE Fix TAP 1 to 7 Adaptation 1'b0
1:1 Enable DFE Fix TAP 8 to 11 Adaptation 1'b0
2:2 Enable VREF Adaptation 1'b1 1'b0
3:3 Enable VGA Adaptation 1'b1 1'b0
4:4 Enable CTLE Adaptation 1'b1 1'b0
0x14B 7:7 Enable CTLE Adaptation 1'b1 1'b0
0x15B 4:4 Enable CTLE Adaptation 1'b1 1'b0
0x15B 0:0 Bypass DFE Fix TAP 1 to 7 Adaptation 1'b1
2:2 Bypass DFE Fix TAP 8 to 11 Adaptation 1'b1
0x15E 0:0 Bypass VREF Adaptations 1'b0 1'b1
0x160 0:0 Bypass VGA Adaptations 1'b1
0x166 0:0 Bypass Single Stage CTLE 1'b0 1'b1
0x167 0:0 Bypass 4 Stage CTLE 1'b0 1'b1
0x163 7:5 CTLE Adaptation Timer Window 3'b111
0x14D 2:0 DFE Adaptation Mode 3'b100 3'b111
0x124 5:5 Enable DFT 1'b1
0x11F 5:4 Eq_bw_sel 2'b01 (Gen3) 2'b00 (Gen1/2)

Refer to the " Arria® 10 Register Map" and "Arria 10 Adaptation Tool" for details on adaptation registers.

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