Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Transceiver PHY Overview 2. Implementing Protocols in Arria 10 Transceivers 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Arria 10 Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Analog Parameter Settings 9. Debugging Transceiver Toolkit
1. Arria® 10 Transceiver PHY Overview x
1.1. Device Transceiver Layout 1.2. Transceiver PHY Architecture Overview 1.3. Calibration 1.4. Arria® 10 Transceiver PHY Overview Revision History
1.1. Device Transceiver Layout x
1.1.1. Arria® 10 GX Device Transceiver Layout 1.1.2. Arria® 10 GT Device Transceiver Layout 1.1.3. Arria® 10 GX and GT Device Package Details 1.1.4. Arria® 10 SX Device Transceiver Layout 1.1.5. Arria® 10 SX Device Package Details
1.2. Transceiver PHY Architecture Overview x
1.2.1. Transceiver Bank Architecture 1.2.2. PHY Layer Transceiver Components 1.2.3. Transceiver Phase-Locked Loops 1.2.4. Clock Generation Block (CGB)
1.2.2. PHY Layer Transceiver Components x
1.2.2.1. The GX Transceiver Channel 1.2.2.2. The GT Transceiver Channel
1.2.3. Transceiver Phase-Locked Loops x
1.2.3.1. Advanced Transmit (ATX) PLL 1.2.3.2. Fractional PLL (fPLL) 1.2.3.3. Channel PLL (CMU/CDR PLL)
2. Implementing Protocols in Arria 10 Transceivers x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Arria® 10 Transceiver Protocols and PHY IP Support 2.4. Using the Arria® 10 Transceiver Native PHY IP Core 2.5. Interlaken 2.6. Ethernet 2.7. PCI Express* (PIPE) 2.8. CPRI 2.9. Other Protocols 2.10. Simulating the Transceiver Native PHY IP Core 2.11. Implementing Protocols in Arria® 10 Transceivers Revision History
2.2. Transceiver Design Flow x
2.2.1. Select and Instantiate the PHY IP Core 2.2.2. Configure the PHY IP Core 2.2.3. Generate the PHY IP Core 2.2.4. Select the PLL IP Core 2.2.5. Configure the PLL IP Core 2.2.6. Generate the PLL IP Core 2.2.7. Reset Controller 2.2.8. Create Reconfiguration Logic 2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller 2.2.10. Connect Datapath 2.2.11. Make Analog Parameter Settings 2.2.12. Compile the Design 2.2.13. Verify Design Functionality
2.4. Using the Arria® 10 Transceiver Native PHY IP Core x
2.4.1. Presets 2.4.2. General and Datapath Parameters 2.4.3. PMA Parameters 2.4.4. Enhanced PCS Parameters 2.4.5. Standard PCS Parameters 2.4.6. PCS Direct 2.4.7. Dynamic Reconfiguration Parameters 2.4.8. PMA Ports 2.4.9. Enhanced PCS Ports 2.4.10. Standard PCS Ports 2.4.11. IP Core File Locations 2.4.12. Unused Transceiver RX Channels 2.4.13. Unsupported Features
2.4.9. Enhanced PCS Ports x
2.4.9.1. Enhanced PCS TX and RX Control Ports
2.5. Interlaken x
2.5.1. Metaframe Format and Framing Layer Control Word 2.5.2. Interlaken Configuration Clocking and Bonding 2.5.3. How to Implement Interlaken in Arria 10 Transceivers 2.5.4. Design Example 2.5.5. Native PHY IP Parameter Settings for Interlaken
2.5.2. Interlaken Configuration Clocking and Bonding x
2.5.2.1. xN Clock Bonding Scenario 2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine x
2.5.2.2.1. TX FIFO Soft Bonding 2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
2.6. Ethernet x
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants 2.6.3. 10GBASE-KR PHY IP Core 2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core 2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.6. XAUI PHY IP Core 2.6.7. Acronyms
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 x
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 2.6.1.4. Rate Match FIFO for GbE 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria® 10 Transceivers 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 x
2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants x
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R 2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers 2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R x
2.6.2.1.1. TX FIFO and RX FIFO
2.6.3. 10GBASE-KR PHY IP Core x
2.6.3.1. 10GBASE-KR PHY Release Information 2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization 2.6.3.3. 10GBASE-KR Functional Description 2.6.3.4. Parameterizing the 10GBASE-KR PHY 2.6.3.5. 10GBASE-KR PHY Interfaces 2.6.3.6. Avalon® Memory-Mapped Interface Registers 2.6.3.7. Creating a 10GBASE-KR Design 2.6.3.8. Design Example 2.6.3.9. Simulation Support
2.6.3.4. Parameterizing the 10GBASE-KR PHY x
2.6.3.4.1. General Options 2.6.3.4.2. 10GBASE-R Parameters 2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters 2.6.3.4.4. 10GBASE-KR Optional Parameters 2.6.3.4.5. Speed Detection Parameters
2.6.3.5. 10GBASE-KR PHY Interfaces x
2.6.3.5.1. Clock and Reset Interfaces 2.6.3.5.2. Data Interfaces 2.6.3.5.3. XGMII Mapping to Standard SDR XGMII Data 2.6.3.5.4. Serial Data Interface 2.6.3.5.5. Control and Status Interfaces 2.6.3.5.6. Dynamic Reconfiguration Interface
2.6.3.6. Avalon® Memory-Mapped Interface Registers x
2.6.3.6.1. 10GBASE-KR PHY Register Definitions 2.6.3.6.2. Hard Transceiver PHY Registers 2.6.3.6.3. Enhanced PCS Registers 2.6.3.6.4. PMA Registers
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core x
2.6.4.1. 1G/10GbE PHY Release Information 2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization 2.6.4.3. 1G/10GbE PHY Functional Description 2.6.4.4. Clock and Reset Interfaces 2.6.4.5. Parameterizing the 1G/10GbE PHY 2.6.4.6. 1G/10GbE PHY Interfaces 2.6.4.7. Avalon® Memory-Mapped Interface Registers 2.6.4.8. Creating a 1G/10GbE Design 2.6.4.9. Design Guidelines 2.6.4.10. Channel Placement Guidelines 2.6.4.11. Design Example 2.6.4.12. Simulation Support 2.6.4.13. TimeQuest Timing Constraints
2.6.4.5. Parameterizing the 1G/10GbE PHY x
2.6.4.5.1. General Options 2.6.4.5.2. 10GBASE-R Parameters 2.6.4.5.3. 10M/100M/1Gb Ethernet Parameters 2.6.4.5.4. Speed Detection Parameters 2.6.4.5.5. PHY Analog Parameters
2.6.4.6. 1G/10GbE PHY Interfaces x
2.6.4.6.1. Clock and Reset Interfaces 2.6.4.6.2. Data Interfaces 2.6.4.6.3. XGMII Mapping to Standard SDR XGMII Data 2.6.4.6.4. GMII Interface 2.6.4.6.5. Serial Data Interface 2.6.4.6.6. Control and Status Interfaces 2.6.4.6.7. MII 2.6.4.6.8. Dynamic Reconfiguration Interface
2.6.4.7. Avalon® Memory-Mapped Interface Registers x
2.6.4.7.1. 1G/10GbE Register Definitions 2.6.4.7.2. Hard Transceiver PHY Registers 2.6.4.7.3. Enhanced PCS Registers 2.6.4.7.4. Arria 10 GMII PCS Registers 2.6.4.7.5. PMA Registers 2.6.4.7.6. Speed Change Summary
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.5.2. Using the IP Core 2.6.5.3. Functional Description 2.6.5.4. Configuration Registers 2.6.5.5. Interface Signals
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1.1. Features 2.6.5.1.2. Release Information 2.6.5.1.3. Device Family Support 2.6.5.1.4. Resource Utilization
2.6.5.2. Using the IP Core x
2.6.5.2.1. Parameter Settings
2.6.5.3. Functional Description x
2.6.5.3.1. Clocking and Reset Sequence 2.6.5.3.2. Timing Constraints 2.6.5.3.3. Switching Operation Speed
2.6.5.4. Configuration Registers x
2.6.5.4.1. Register Map 2.6.5.4.2. Configuration Registers
2.6.5.5. Interface Signals x
2.6.5.5.1. Clock and Reset Signals 2.6.5.5.2. Operating Mode and Speed Signals 2.6.5.5.3. GMII Signals 2.6.5.5.4. XGMII Signals 2.6.5.5.5. Status Signals 2.6.5.5.6. Serial Interface Signals 2.6.5.5.7. Transceiver Status and Reconfiguration Signals 2.6.5.5.8. Avalon® Memory-Mapped Interface Signals
2.6.6. XAUI PHY IP Core x
2.6.6.1. Transceiver Datapath in a XAUI Configuration 2.6.6.2. XAUI Supported Features 2.6.6.3. XAUI PHY Release Information 2.6.6.4. XAUI PHY Device Family Support 2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration 2.6.6.6. XAUI PHY Performance and Resource Utilization 2.6.6.7. Parameterizing the XAUI PHY 2.6.6.8. XAUI PHY Ports 2.6.6.9. XAUI PHY Interfaces 2.6.6.10. XAUI PHY Register Interface and Register Descriptions 2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint
2.6.6.7. Parameterizing the XAUI PHY x
2.6.6.7.1. XAUI PHY General Parameters 2.6.6.7.2. XAUI PHY Advanced Options Parameters
2.6.6.9. XAUI PHY Interfaces x
2.6.6.9.1. SDR XGMII TX Interface 2.6.6.9.2. SDR XGMII RX Interface 2.6.6.9.3. Transceiver Serial Data Interface 2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces 2.6.6.9.5. XAUI PHY PMA Channel Controller Interface 2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface
2.7. PCI Express* (PIPE) x
2.7.1. Transceiver Channel Datapath for PIPE 2.7.2. Supported PIPE Features 2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2.7.4. How to Implement PCI Express* (PIPE) in Arria 10 Transceivers 2.7.5. Native PHY IP Parameter Settings for PIPE 2.7.6. fPLL IP Parameter Core Settings for PIPE 2.7.7. ATX PLL IP Parameter Core Settings for PIPE 2.7.8. Native PHY IP Ports for PIPE 2.7.9. fPLL Ports for PIPE 2.7.10. ATX PLL Ports for PIPE 2.7.11. Preset Mappings to TX De-emphasis 2.7.12. How to Place Channels for PIPE Configurations 2.7.13. PHY IP Core for PCIe* (PIPE) Link Equalization for Gen3 Data Rate 2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration Interface to manually tune Arria® 10 PCIe designs (Hard IP(HIP) and PIPE) (For debug only)
2.7.2. Supported PIPE Features x
2.7.2.1. Gen1/Gen2 Features 2.7.2.2. Gen3 Features
2.7.2.1. Gen1/Gen2 Features x
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) 2.7.2.1.2. Transmitter Electrical Idle Generation 2.7.2.1.3. Power State Management 2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 2.7.2.1.5. Receiver Status 2.7.2.1.6. Receiver Detection 2.7.2.1.7. Gen1 and Gen2 Clock Compensation 2.7.2.1.8. PCIe* Reverse Parallel Loopback
2.7.2.2. Gen3 Features x
2.7.2.2.1. Auto-Speed Negotiation 2.7.2.2.2. Rate Switch 2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation 2.7.2.2.4. Gen3 Clock Compensation 2.7.2.2.5. Gen3 Power State Management 2.7.2.2.6. CDR Control 2.7.2.2.7. Gearbox
2.7.12. How to Place Channels for PIPE Configurations x
2.7.12.1. Master Channel in Bonded Configurations
2.8. CPRI x
2.8.1. Transceiver Channel Datapath and Clocking for CPRI 2.8.2. Supported Features for CPRI 2.8.3. Word Aligner in Manual Mode for CPRI 2.8.4. How to Implement CPRI in Arria® 10 Transceivers 2.8.5. Native PHY IP Parameter Settings for CPRI
2.8.1. Transceiver Channel Datapath and Clocking for CPRI x
2.8.1.1. TX PLL Selection for CPRI 2.8.1.2. Auto-Negotiation
2.8.2. Supported Features for CPRI x
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI x
2.8.2.1.1. Transmitter and Receiver Latency
2.9. Other Protocols x
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS 2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS 2.9.3. Design Considerations for Implementing Arria 10 GT Channels 2.9.4. How to Implement PCS Direct Transceiver Configuration Rule
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS x
2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules in Arria 10 Transceivers 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS 2.9.1.4. Enhanced PCS FIFO Operation 2.9.1.5. TX Data Bitslip 2.9.1.6. TX Data Polarity Inversion 2.9.1.7. RX Data Bitslip 2.9.1.8. RX Data Polarity Inversion
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS x
2.9.2.1. Word Aligner Manual Mode 2.9.2.2. Word Aligner Synchronous State Machine Mode 2.9.2.3. RX Bit Slip 2.9.2.4. RX Polarity Inversion 2.9.2.5. RX Bit Reversal 2.9.2.6. RX Byte Reversal 2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode 2.9.2.8. Rate Match FIFO Basic (Double Width) Mode 2.9.2.9. 8B/10B Encoder and Decoder 2.9.2.10. 8B/10B TX Disparity Control 2.9.2.11. How to Enable Low Latency in Basic 2.9.2.12. TX Bit Slip 2.9.2.13. TX Polarity Inversion 2.9.2.14. TX Bit Reversal 2.9.2.15. TX Byte Reversal 2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria® 10 Transceivers 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
2.9.3. Design Considerations for Implementing Arria 10 GT Channels x
2.9.3.1. Transceiver PHY IP 2.9.3.2. PLL and GT Transceiver Channel Clock Lines 2.9.3.3. Reset Controller 2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode 2.9.3.5. Arria 10 GT Channel Usage
2.10. Simulating the Transceiver Native PHY IP Core x
2.10.1. NativeLink Simulation Flow 2.10.2. Scripting IP Simulation 2.10.3. Custom Simulation Flow
2.10.1. NativeLink Simulation Flow x
2.10.1.1. How to Use NativeLink to Specify a ModelSim* Simulation 2.10.1.2. How to Use NativeLink to Run a ModelSim* RTL Simulation 2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators
2.10.2. Scripting IP Simulation x
2.10.2.1. Generating a Combined Simulator Setup Script
2.10.3. Custom Simulation Flow x
2.10.3.1. How to Use the Simulation Library Compiler 2.10.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Transmitter Data Path Interface Clocking 3.7. Receiver Data Path Interface Clocking 3.8. Unused/Idle Clock Line Requirements 3.9. Channel Bonding 3.10. PLL Feedback and Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs 3.1.2. ATX PLL 3.1.3. fPLL 3.1.4. CMU PLL
3.1.2. ATX PLL x
3.1.2.1. Instantiating the ATX PLL IP Core 3.1.2.2. ATX PLL IP Core
3.1.3. fPLL x
3.1.3.1. Instantiating the fPLL IP Core 3.1.3.2. fPLL IP Core
3.1.4. CMU PLL x
3.1.4.1. Instantiating CMU PLL IP Core 3.1.4.2. CMU PLL IP Core
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Global Clock or Core Clock as an Input Reference Clock
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. xN Clock Lines 3.3.4. GT Clock Lines
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. PCS Bonding Channels Placement Restrictions 3.9.4. Selecting Channel Bonding Schemes 3.9.5. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/xN Bonding 3.9.1.2. PLL Feedback Compensation Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Mix and Match Example 3.11.5. Timing Closure Recommendations
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/xN Bonding Mode 3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Implementation 4.3. How Do I Reset? 4.4. Using the Transceiver PHY Reset Controller 4.5. Using a User-Coded Reset Controller 4.6. Combining Status or PLL Lock Signals 4.7. Timing Constraints for Bonded PCS and PMA Channels 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Model 1: Default Model 4.3.2. Model 2: Acknowledgment Model 4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
4.3.1. Model 1: Default Model x
4.3.1.1. Recommended Reset Sequence 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver During Device Operation 4.3.1.4. Resetting the Transceiver Channel During Device Operation 4.3.1.5. Dynamic Reconfiguration of Channel Using the Default Model
4.3.2. Model 2: Acknowledgment Model x
4.3.2.1. Recommended Reset Sequence 4.3.2.2. Resetting the Transmitter During Device Operation 4.3.2.3. Resetting the Receiver During Device Operation 4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model 4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
4.4. Using the Transceiver PHY Reset Controller x
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP 4.4.2. Transceiver PHY Reset Controller Parameters 4.4.3. Transceiver PHY Reset Controller Interfaces 4.4.4. Transceiver PHY Reset Controller Resource Utilization
4.5. Using a User-Coded Reset Controller x
4.5.1. User-Coded Reset Controller Signals
5. Arria 10 Transceiver PHY Architecture x
5.1. Arria® 10 PMA Architecture 5.2. Arria 10 Enhanced PCS Architecture 5.3. Arria® 10 Standard PCS Architecture 5.4. Arria 10 PCI Express* Gen3 PCS Architecture 5.5. Arria® 10 Transceiver PHY Architecture Revision History
5.1. Arria® 10 PMA Architecture x
5.1.1. Transmitter 5.1.2. Serializer 5.1.3. Transmitter Buffer 5.1.4. Receiver 5.1.5. Receiver Buffer 5.1.6. Clock Data Recovery (CDR) Unit 5.1.7. Deserializer 5.1.8. Loopback
5.1.3. Transmitter Buffer x
5.1.3.1. High Speed Differential I/O 5.1.3.2. Programmable Output Differential Voltage 5.1.3.3. Programmable Pre-Emphasis 5.1.3.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation 5.1.3.5. Programmable Transmitter On-Chip Termination (OCT)
5.1.5. Receiver Buffer x
5.1.5.1. Programmable Common Mode Voltage (VCM) 5.1.5.2. Programmable Differential On-Chip Termination (OCT) 5.1.5.3. Signal Detector 5.1.5.4. Continuous Time Linear Equalization (CTLE) 5.1.5.5. Variable Gain Amplifier (VGA) 5.1.5.6. Decision Feedback Equalization (DFE) 5.1.5.7. How to Enable CTLE and DFE
5.1.6. Clock Data Recovery (CDR) Unit x
5.1.6.1. Lock-to-Reference Mode 5.1.6.2. Lock-to-Data Mode 5.1.6.3. CDR Lock Modes
5.2. Arria 10 Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath
5.2.1. Transmitter Datapath x
5.2.1.1. Enhanced PCS TX FIFO 5.2.1.2. Interlaken Frame Generator 5.2.1.3. Interlaken CRC-32 Generator 5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.5. Pattern Generators 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion 5.2.1.9. KR FEC Blocks
5.2.1.1. Enhanced PCS TX FIFO x
5.2.1.1.1. Phase Compensation Mode 5.2.1.1.2. Register Mode 5.2.1.1.3. Interlaken Mode 5.2.1.1.4. Basic Mode
5.2.1.5. Pattern Generators x
5.2.1.5.1. PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS) 5.2.1.5.2. Pseudo-Random Pattern Generator
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. Pseudo Random Pattern Verifier 5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.9. Interlaken CRC-32 Checker 5.2.2.10. Enhanced PCS RX FIFO 5.2.2.11. RX KR FEC Blocks
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) x
5.2.2.6.1. PRBS Checker
5.2.2.10. Enhanced PCS RX FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Interlaken Mode 5.2.2.10.4. 10GBASE-R Mode 5.2.2.10.5. Basic Mode
5.3. Arria® 10 Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) 5.3.1.2. Byte Serializer 5.3.1.3. 8B/10B Encoder 5.3.1.4. Polarity Inversion Feature 5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator 5.3.1.6. TX Bit Slip
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.1.1.1. TX FIFO Low Latency Mode 5.3.1.1.2. TX FIFO Register Mode 5.3.1.1.3. TX FIFO Fast Register Mode
5.3.1.2. Byte Serializer x
5.3.1.2.1. Bonded Byte Serializer 5.3.1.2.2. Byte Serializer Disabled Mode 5.3.1.2.3. Byte Serializer Serialize x2 Mode 5.3.1.2.4. Byte Serializer Serialize x4 Mode
5.3.1.3. 8B/10B Encoder x
5.3.1.3.1. 8B/10B Encoder Control Code Encoding 5.3.1.3.2. 8B/10B Encoder Reset Condition 5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. Pseudo-Random Binary Sequence (PRBS) Checker 5.3.2.6. Byte Deserializer 5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bit Slip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer
5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.2.7.1. RX FIFO Low Latency Mode 5.3.2.7.2. RX FIFO Register Mode
5.4. Arria 10 PCI Express* Gen3 PCS Architecture x
5.4.1. Transmitter Datapath 5.4.2. Receiver Datapath 5.4.3. PIPE Interface
5.4.1. Transmitter Datapath x
5.4.1.1. TX FIFO (Shared with Standard and Enhanced PCS) 5.4.1.2. Gearbox
5.4.2. Receiver Datapath x
5.4.2.1. Block Synchronizer 5.4.2.2. Rate Match FIFO 5.4.2.3. RX FIFO (Shared with Standard and Enhanced PCS)
5.4.3. PIPE Interface x
5.4.3.1. Auto Speed Negotiation 5.4.3.2. Clock Data Recovery Control
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Configuration Files 6.4. Multiple Reconfiguration Profiles 6.5. Embedded Reconfiguration Streamer 6.6. Arbitration 6.7. Recommendations for Dynamic Reconfiguration 6.8. Steps to Perform Dynamic Reconfiguration 6.9. Direct Reconfiguration Flow 6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.11. Reconfiguration Flow for Special Cases 6.12. Changing PMA Analog Parameters 6.13. Ports and Parameters 6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.15. Embedded Debug Features 6.16. Using Data Pattern Generators and Checkers 6.17. Timing Closure Recommendations 6.18. Unsupported Features 6.19. Arria® 10 Transceiver Register Map 6.20. Reconfiguration Interface and Dynamic Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.11. Reconfiguration Flow for Special Cases x
6.11.1. Switching Transmitter PLL 6.11.2. Switching Reference Clocks
6.11.2. Switching Reference Clocks x
6.11.2.1. ATX Reference Clock Switching 6.11.2.2. fPLL Reference Clock Switching 6.11.2.3. CDR and CMU Reference Clock Switching
6.12. Changing PMA Analog Parameters x
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow 6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow 6.12.3. CTLE Settings in Triggered Adaptation Mode 6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow
6.15. Embedded Debug Features x
6.15.1. Native PHY Debug Master Endpoint 6.15.2. Optional Reconfiguration Logic
6.15.2. Optional Reconfiguration Logic x
6.15.2.1. Capability Registers 6.15.2.2. Control and Status Registers 6.15.2.3. PRBS Soft Accumulators
6.16. Using Data Pattern Generators and Checkers x
6.16.1. Using PRBS Data Pattern Generator and Checker 6.16.2. Using Pseudo Random Pattern Mode
6.16.1. Using PRBS Data Pattern Generator and Checker x
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs 6.16.1.2. Enabling the PRBS Data Generator in bonded designs 6.16.1.3. Enabling the PRBS Data Checker in non bonded design 6.16.1.4. Enabling the PRBS Checker in bonded designs 6.16.1.5. Disabling/Enabling PRBS Pattern Inversion
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs x
6.16.1.1.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in non bonded designs
6.16.1.2. Enabling the PRBS Data Generator in bonded designs x
6.16.1.2.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in bonded designs
6.16.1.3. Enabling the PRBS Data Checker in non bonded design x
6.16.1.3.1. Examples of Enabling the PRBS Data Checker
6.16.2. Using Pseudo Random Pattern Mode x
6.16.2.1. Enabling Pseudo Random Pattern Mode
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. User Recalibration 7.5. Calibration Example 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. Transceiver Channel Calibration Registers 7.2.3. Fractional PLL Calibration Registers 7.2.4. ATX PLL Calibration Registers 7.2.5. Capability Registers 7.2.6. Rate Switch Flag Register
7.4. User Recalibration x
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change x
7.4.1.1. User Recalibration
7.5. Calibration Example x
7.5.1. ATX PLL Recalibration 7.5.2. Fractional PLL Recalibration 7.5.3. CDR/CMU PLL Recalibration 7.5.4. PMA Recalibration
8. Analog Parameter Settings x
8.1. Making Analog Parameter Settings using the Assignment Editor 8.2. Updating Quartus Settings File with the Known Assignment 8.3. Analog Parameter Settings List 8.4. Receiver General Analog Settings 8.5. Receiver Analog Equalization Settings 8.6. Transmitter General Analog Settings 8.7. Transmitter Pre-Emphasis Analog Settings 8.8. Transmitter VOD Settings 8.9. Dedicated Reference Clock Settings 8.10. Unused Transceiver RX Channels Settings 8.11. Analog Parameter Settings Revision History
8.4. Receiver General Analog Settings x
8.4.1. XCVR_A10_RX_LINK 8.4.2. XCVR_A10_RX_TERM_SEL 8.4.3. XCVR_VCCR_VCCT_VOLTAGE - RX
8.5. Receiver Analog Equalization Settings x
8.5.1. CTLE Settings 8.5.2. VGA Settings 8.5.3. Decision Feedback Equalizer (DFE) Settings
8.5.1. CTLE Settings x
8.5.1.1. XCVR_A10_RX_ONE_STAGE_ENABLE 8.5.1.2. XCVR_A10_RX_EQ_DC_GAIN_TRIM 8.5.1.3. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 8.5.1.4. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
8.5.2. VGA Settings x
8.5.2.1. XCVR_A10_RX_ADP_VGA_SEL
8.5.3. Decision Feedback Equalizer (DFE) Settings x
8.5.3.1. XCVR_A10_RX_ADP_DFE_FXTAP
8.6. Transmitter General Analog Settings x
8.6.1. XCVR_A10_TX_LINK 8.6.2. XCVR_A10_TX_TERM_SEL 8.6.3. XCVR_A10_TX_COMPENSATION_EN 8.6.4. XCVR_VCCR_VCCT_VOLTAGE - TX 8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL
8.7. Transmitter Pre-Emphasis Analog Settings x
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T 8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T 8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP 8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP 8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
8.8. Transmitter VOD Settings x
8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
8.9. Dedicated Reference Clock Settings x
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE 8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE
9. Debugging Transceiver Toolkit x
9.1. Transceiver Toolkit GUI 9.2. Transceiver Debugging Flow Walkthrough 9.3. Linking Hardware Resource for Multiple FPGAs 9.4. Troubleshooting Common Errors 9.5. Debugging Transceiver Toolkit Revision History
9.1. Transceiver Toolkit GUI x
9.1.1. Main View Functions
9.2. Transceiver Debugging Flow Walkthrough x
9.2.1. Enabling Transceiver Toolkit Support 9.2.2. Programming Design into an Intel® FPGA 9.2.3. Loading Design to the Transceiver Toolkit 9.2.4. Creating Transceiver Links 9.2.5. Running Link Test
9.2.4. Creating Transceiver Links x
9.2.4.1. Transceiver Toolkit Parameter Settings 9.2.4.2. Verifying Hardware Connections
9.2.5. Running Link Test x
9.2.5.1. Running BER Tests 9.2.5.2. Link Optimization Tests
9.3. Linking Hardware Resource for Multiple FPGAs x
9.3.1. Linking One Design to One Device 9.3.2. Linking Two Designs to Two Devices 9.3.3. Linking One Design on Two Devices 9.3.4. Linking Designs and Devices on Separate Boards
1. Arria® 10 Transceiver PHY Overview
2. Implementing Protocols in Arria 10 Transceivers
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Arria 10 Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Analog Parameter Settings
9. Debugging Transceiver Toolkit

2.11. Implementing Protocols in Arria® 10 Transceivers Revision History

Document Version Changes
2024.04.01
  • Updated Nios II Calibration IP to Nios Hard Calibration IP in figures: Native PHY IP Core Ports and Functional Blocks and Signals and Ports of Native PHY IP for PIPE.
  • Updated Nios II Sequencer Interface to Nios V Sequencer Interface in figure 10GBASE-KR PHY IP Core Block Diagram.
2022.03.28 Updated descriptions for the Enable KR-FEC TX error insertion and KR-FEC TX error insertion spacing parameters in the KR-FEC Parameters table.
2022.02.08
  • Updated the clock width for tx_pma_clkout[<n>-1:0] and tx_pma_div_clkout[<n>-1:0] in the TX PMA Ports table.
  • Updated the clock width for rx_pma_clkout[<n>-1:0] and rx_pma_div_clkout[<n>-1:0] in the RX PMA Ports table.
  • Updated the clock width for tx_coreclkin[<n>-1:0], tx_clkout[<n>-1:0], rx_coreclkin[<n>-1:0], and rx_clkout[<n>-1:0] in the Enhanced TX PCS: Parallel Data, Control, and Clocks table.
  • Updated the clock width for tx_coreclkin[<n>-1:0] and tx_clkout[<n>-1:0] in the TX Standard PCS: Data, Control, and Clocks table.
  • Updated the clock width for rx_coreclkin[<n>-1:0] and rx_clkout[<n>-1:0] in the RX Standard PCS: Data, Control, and Clocks table.
2021.08.05
  • Updated the descriptions for TX FIFO Mode, Enable tx_enh_fifo_empty port and Enable tx_enh_fifo_pempty port parameters in the Enhanced PCS TX FIFO Parameters table.
  • Updated the descriptions for RX FIFO Mode , Enable rx_enh_fifo_full port , and Enable rx_enh_fifo_pfull port parameters in the Enhanced PCS RX FIFO Parameters table.
  • Updated the clock domains for tx_enh_fifo_full[<n>-1:0], tx_enh_fifo_pfull[<n>-1:0], tx_enh_fifo_empty[<n>-1:0], and tx_enh_fifo_pempty[<n>-1:0] in the Enhanced PCS TX FIFO table.
  • Updated the clock domains for rx_enh_fifo_full[<n>-1:0], rx_enh_fifo_pfull[<n>-1:0], rx_enh_fifo_empty[<n>-1:0], and rx_enh_fifo_pempty[<n>-1:0] in the Enhanced PCS RX FIFO table.
  • Removed references to the NCSim simulator.
2021.06.10
  • Updated description for Enable tx_pma_div_clkout port parameter in the TX PMA Optional Ports table.
  • Updated the reference for Soft Enhanced PCS FIFO for IEEE 1588v2 in the 1G/10GbE PHY Functional Description section.
  • Updated the Quartus® Prime subdirectory and links in the Design Example section.
2021.01.29 Made the following change:
  • Clarified that the rx_pma_clkslip falling edge makes the RX deserializer bit slip the serial data by one UI.
2020.05.08 Made the following change:
  • Confirmed that the XAUI PHY support model is final in the "Device Family Support" table.
2019.12.13 Made the following changes to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core" section:
  • Updated the Clocking and Reset Sequence topic to state that the 1G/ 2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core for Cyclone® 10 GX devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.
2019.11.04 Made the following change:
  • Clarified which counters are cleared by 0x481 in Enhanced PCS Registers.
2019.06.12 Made the following change:
  • Clarified that the Enhanced PCS only supports the static polarity inversion feature, but the Standard PCS supports both the static and dynamic polarity inversion features.
2019.05.13 Made the following change:
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY DebugMaster Endpoint (NPDME).
2019.01.30

Made the following change to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core section:

  • Updated Table: Clock and Reset Signals to update the description for rx_pma_clkout.
2018.10.16 Made the following change:
  • For PRESERVE_UNUSED_XCVR_CHANNEL, clarified that an example of <pin_name> is U34, not PIN_U34.
2018.09.24

Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core section:

  • Added Functional Description section.
  • Updated the note in About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core topic.
  • For the 1G/2.5G/5G/10G Multi-rate Ethernet status signal, added a Clock Domain values for led_char_err.
  • Added 10M and 100M speed support for 1G/2.5G/5G/10G (USXGMII) variant for 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core.
  • Updated the Device Family Support section:
    • Removed the description on Definition: Device Support Level.
    • Added a new Table: Intel FPGA Core Device Support Levels.
  • Updated Table: Resource Utilization.
  • Updated Timing Constraints section.
  • Updated Configuration Registers section:
    • Added Register Access section.
    • Removed Definition: Register Access section.
  • Updated Figure: PHY Interface Signals.
  • Updated Table: XGMII Signals:
    • Corrected the direction of xgmii_tx_valid.
    • Updated the toggle rate of 10G speed for xgmii_tx_valid and xgmii_rx_valid.
  • Updated for latest Intel branding standards.
2018.06.15

Made the following changes:

  • For the 1G/2.5G/5G/10G Multi-rate Ethernet status signal, added a Clock Domain column and values for all except led_char_err.
  • Changed the Gen1 PIPE PLL output frequency from 1250MHz to 2500MHz in fPLL IP Parameter Core Settings for PIPE and ATX PLL IP Parameter Core Settings for PIPE.
  • Updated Disabling/Enabling PRBS Pattern Inversion to address the hard PRBS generator and checker pattern being inverted.
  • Updated the description of 0x4C0 bit 5 Override AN Parameters Enable to refer to 0x4C3 and changed the start address of the reserved space to 0x4D7 in 10GBASE-KR PHY Register Definitions.
  • Changed the start address of the reserved space to 0x4D7 in 1G/10GbE Register Definitions.
  • Added a frequency to the description of and added a footnote to the Selected CDR reference clock frequency parameter in the "RX PMA Parameters" table.
  • Added a note about bit slipping after the "Gearbox Parameters" table.
  • Added a reference and a link to Clock and Reset Interfaces in the "1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core" section.
  • Clarified the description of the Enable PCIe pipe_hclk_in and pipe_hclk_out ports parameter in the "PCIe Ports" table.
  • Clarified the description of the pipe_hclk_out[0] port in the "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table.
  • Changed the values for the Number of fixed dfe taps parameter in the "RX PMA Parameters" table of the Interlaken section.
  • Changed the description of bit 15 of register address 0x4D0 in the "1G/10GbE Register Definitions" table.
  • Changed the description of bit 5 of register address 0x4C0 in the "1G/10GbE Register Definitions" table.
2017.11.06

Made the following changes to the CPRI section:

  • Removed a note from the "Transmitter and Receiver Latency" section.

Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:

  • Added the "Register Map" section.
2016.10.31

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

  • Added MII Interface signals to the "1G/10GbE PHY Top-Level Signals" figure.
  • Added the MII section.
  • Added the tx_pcfifo_error_1g and rx_pcfifo_error_1g signals to the "Control and Status Signals" table.
  • Removed bit addresses from the 0x494 register in the "GMII PCS Registers" table.
  • Changed the read/write description for the 0x495 register in the "GMII PCS Registers" table.
  • Changed the note for COPPER_DUPLEX_OPERATION in the "GMII PCS Registers" table.

Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:

  • Added description about the RX FIFO and TX FIFO in the "GbE with IEEE 1588v2" section.
  • Added a note to the pll_powerdown signal in the "Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design" figure.
  • Updated the parameter descriptions for in the "Standard PCS Parameters" table.

Made the following changes to the XAUI PHY IP Core section:

  • Added further description to the rx_channelaligned signal in the "Optional Control and Status Signals—Soft IP Implementation" table.

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:

  • Added "Synchronous to rx_clkout" for rx_std_wa_patternalign[<n>-1:0] in the clock domain column in Word Aligner and Bitslip table.
  • Added "Unused Transceiver Channels" section.

Made the following changes to the CPRI section:

  • New table "Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates" added.
  • Supported data rates updated for TX PLLs.
  • Data rate values updated in table "General and Datapath Options".

Made the following changes to the PCI Express section:

  • Added PIPE Interface width number in the Port column in table "Ports for Arria 10 Transceiver Native PHY in PIPE Mode".
2016.05.02

Made the following changes to the 10GBASE-KR PHY IP Core section:

  • Updated the version and release date in the "10GBASE-KR PHY Release Information" table.
  • Changed the definitions and parameters in the "General Options Parameters" table.
  • Added the "Speed Detection Parameters" table.
  • Added and removed parameters in the "Auto Negotiation and Link Training Settings" table.
  • Removed parameter from the "10GBASE-R Parameters" table.
  • Changed descriptions in the "10GBASE-KR Register Definitions" table for 0x4B0 and 0x4D0.
  • Added signals to the "Control and Status Signals" table.
  • Added a new bit field for 0x4D1 in the "10GBASE-KR Register Definitions" table.
  • Changed the default value for INITPOSTVAL Init Post tap Value in the "10GBASE-KR Optional Parameters" table.

Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:

  • Changed the "Block Diagram of the PHY IP Core" figure.
  • Updated the version and release date in the "PHY Release Information" table.
  • Updated the "Resource Utilization" table.
  • Updated the "PHY Features" table.
  • Changed the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.
  • Added signals to the "PHY Interface Signals" figure.
  • Added descriptions in the "Clock and Reset Signals" table.
  • Added descriptions in the "Transceiver Mode and Operating Speed Signals" table.
  • Changed the " Avalon® Memory-Mapped Interface Signals" table.
  • Added signals to the "XGMII Signals" table.
  • Added registers to the "PHY Register Definitions" table.
  • Added parameters to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.

Made the following changes to the 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core section:

  • Updated the version and release date in the "1G/10GbE Release Information" table.
  • Added signals to the "1G/10GbE PHY Top-Level Signals" figure.
  • Added signals to the "PHY Interface Signals" figure.
  • Added signals to the "Control and Status Signals" table.
  • Changed descriptions in the "GMII Interface Ports " table.

Made the following changes to the Simulating the Transceiver Native PHY IP section:

  • Added a footnote to inform that the "NativeLink" mode is not supported by the "Quartus Prime Pro" edition.
  • Added the “Scripting IP Simulation” flow..
  • Replaced the “Generation Version Agnostic IP" and " Platform Designer Platform Designer Simulation Scripts", “Use the ip-make-simscript Utility”, and “How to Generate Scripts” sections with the “Scripting IP Simulation” section.

Made the following changes to the PCI Express section:

  • Updated the "How to Place Channels for PIPE Configuration" section.
  • Updated the“x4 Configuration with Master Channel Adjacent to a HIP”, “x4 Configuration with Master Channel not Adjacent to a HIP”, “Rate Switch Change” figures.

Made the following changes to the Other Protocols section:

  • Replaced the "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” section.
  • Changed the title from "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” to "Design Considerations for implementing Arria 10 GT Channels”.
  • Changed the data rate from a range of “17.4 Gbps to 28.3 Gbps” to 25.78125 Gbps.
  • Changed the titles of “Valid Permutations for GT and GX Channel Configuration in Transceiver Bank GXBL1G for Channels 0, 1, and 2” and “Valid Permutations for GT and GX Channel Configuration in Transceiver Banks GXBL1E and GXBL1H for Channels 3, 4, and 5".
  • Removed the “Native PHY IP Parameter Settings for PCS Direct Transceiver Configuration Rules” section.
  • Changed “How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode” section.
  • Changed the “ATX PLL IP with GT Clock Lines Enabled” figure.
  • Updated the "Valid Permutations for GT and GX Channel Configuration in Transceiver Bank GXBL1G for Channels 0, 1, and 2" and "Valid Permutations for GT and GX Channel Configuration in Transceiver Banks GXBL1E, and GXBL1H for Channels 3, 4, and 5"" tables.

Made the following changes to the CPRI section:

  • Updated the "Transceiver Channel Datapath and Clocking for CPRI" figure.
  • Added a note in the "Channel Width Options for Supported Serial Data Rates" table.
  • Changed the fPLL supported data rate in the "TX PLL Supported Data Rates" table.
  • Changed the "General and Datapath Options" table in the "Native PHY IP Parameter Settings for CPRI" section.

Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:

  • Moved the 19th footnote from "Protocol Preset" column to "Transceiver PHY IP Core" column.
  • Changed the footnote 14 to the following: “Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP”.
2016.02.11

Made the following changes to the Other Protocols section:

  • Removed the "Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels" section.
  • Updated the maximum data rate for GT channels to 25.8 Gbps.
2015.12.18

Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:

  • Removed signals from the "XGMII Signals" table.
  • Removed signals from the "PHY Interface Signals" figure.
  • Changed the ordering code in the "PHY Release Information" table.

Made the following changes to the XAUI PHY IP Core section:

  • Added a description to the "Implementation of the XGMII Specification in Arria 10 Devices Configuration" figure.

Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:

  • Added a note to the "Parameterizing the 10GBASE-KR PHY" section.
  • Added new signals to the "Control and Status Signals" table.

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

  • Added a note to the "Parameterizing the 1G/10GbE PHY" section.
  • Added new signals to the "Control and Status Signals" table.
  • Changed the description for calc_clk_1g in the "Clock and Reset Signals" table.

Made the following changes to the PCI Express (PIPE) section:

  • Updated the "Rate Switch Change" figure in the Gen3 features section.
2015.11.02

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:

  • Changed the title of “TX and RX FIFO” to “Standard PCS FIFO” in the Standard PCS Ports table.
  • Updated the description and range for “Enable fast sync status reporting for deterministic Latency SM” parameter in the Standard PCS Parameters table.
  • Changed the title of “TX and RX FIFO Parameters” to “Standard PCS FIFO Parameters” in the Standard PCS Parameters table.
  • Updated the “Error marking type” range in the KR-FEC Parameters table in the Enhanced PCS Parameters section.
  • Updated the “Number of fixed DFE taps” value in the Equalization table in the PMA Parameters section.
  • Added a new parameter “Provide separate interface for each channel” in the General and Datapath Options table in the General and Datapath Parameters section.
  • Updated the “PMA configuration rules” value in the General and Datapath Options table in the General and Datapath Parameters section.
  • Removed footnote and added "Hard IP for PCI Express to Native PHY IP" in the “Arria 10 Transceiver Protocols and PHY IP Support” table.
  • Updated the description for “Enable tx_pma_ rxfound port (QPI)” parameter in the TX PMA Optional Ports table in the PMA Parameters section.
  • Updated the descriptions for “TX FIFO Mode”,“Enable tx_enh_fifo_full port”, “Enable tx_enh_fifo_empty port” parameters in the Enhanced PCS TX FIFO Parameters table in the Enhanced PCS Parameters section.
  • Updated the descriptions for “Enable rx_enh_fifo_full port”, “Enable rx_enh_fifo_empty port” parameters in the Enhanced PCS RX FIFO Parameters table in the Enhanced PCS Parameters section.
  • Updated the description for “Enable RX byte deserializer” parameter in the Byte Serializer and Deserializer Parameters table in the Standard PCS Parameters section.
  • Updated the description for “Share reconfiguration interface” parameter in the Dynamic Reconfiguration table in the Dynamic Reconfiguration Parameters section.
  • Updated the values and descriptions in the Configuration Profiles table in the Dynamic Reconfiguration Parameters section.
  • Updated the foot note for “tx_pma_clkout” clock to suggest what to do with the clock.
  • Updated the description for “tx_dispval[<n>(<w>/<s>-1:0]” signal in the 8B/10B Encoder and Decoder table in the Standard PCS Ports section.
  • Updated the values and descriptions in the Configuration Profiles table in the Dynamic Reconfiguration Parameters section.
  • Updated the descriptions for “Enable tx_std_ pcfifo_full port”, “Enable tx_std_ pcfifo_empty port”, “Enable rx_std_ pcfifo_full port”, “Enable rx_std_ pcfifo_empty port” in the TX and RX FIFO Parameters table in the Standard PCS Parameters section.
  • Added links to other sections which describe the RX rate match FIFO in Basic, GBE and Transceiver channel datapath modes in the Rate Match FIFO Parameters table in the Standard PCS Parameters section.
  • Updated value for Transceiver Configuration rules parameter in the " General and Datapath Options" table in the General and Datapath Parameters section.
  • Added a new parameter "Provide separate interface for each channel" in the " General and Datapath Options" table in the General and Datapath Parameters section.
  • Updated “Transceiver Native PHY IP Core Parameter Editor” figure.
  • Updated “General, Common PMA Options, and Datapath Options” table.
  • Added parameter “Enable tx_pma_analog_reset_ackport” in “TX PMA Optional Ports” table.
  • Updated parameter “Number of fixed DFE taps” in "Equalization" table.
  • Added parameter “Enable rx_analog_reset_ack port” in "RX PMA Optional Ports” table.
  • Added parameter Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE in “Dynamic Reconfiguration” table.
  • Added parameter “Include PMA analog settings in configuration Files”in “Configuration Files”.
  • Added “Analog PMA Settings (Optional) in Dynamic Reconfiguration” tabl.e

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

  • Changed the release date and version in the "1G/10GbE Release Information" table.
  • Changed the descriptions for tx_serial_clk_1g and rx_cdr_refclk_1g in the "Clock and Reset Signals" table.
  • Changed descriptions in the "General Options Parameters" table.
  • Added the "1G Data Mode" table to the PMA Registers section.
  • Removed the "1G Data Mode" rows from the Arria 10 GMII PCS Registers section.

Made the following changes to the 10GBASE-KR PHY IP Core with FEC Option section:

  • Added bit 12 to the 0x4B0 word address in the "10GBASE-KR Register Definitions" table.

Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:

  • Added a note to the "Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.
  • Changed the note in the "Gigabit Ethernet (GbE) and GbE with IEEE 1588v2" section.
  • Changed some signal names in the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.
  • Changed the values in the "TX PMA Parameters" table.
  • Added a parameter to and updated values in the "RX PMA Parameters" table.
  • Changed the values in the "Standard PCS Parameters" table.

Made the following changes to the 10GBASE-R section:

  • Added description text to the "10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants" section.
  • Changed steps in the "How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers" section.
  • Changed signal names in the "Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
  • Updated parameters in the "General and Datapath Parameters" table.
  • Updated parameters in the "RX PMA Parameters" table.
  • Updated parameters in the "Enhanced PCS Parameters" table.
  • Updated parameters in the "Block Sync Parameters" table.
  • Updated parameters in the "Dynamic Reconfiguration Parameters" table.

Made the following changes to the XAUI PHY IP Core section:

  • Changed the release date and version in the "XAUI Release Information" table.
  • Changed the descriptions in the "XAUI PHY IP Core Registers" table.
  • Added description in the "XAUI PHY IP Core" section.

Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:

  • Added this section.

Made the following changes to the PCI Express (PIPE) section:

  • Updated description for port "pipe_g3_txdeemph[17:0]" in the "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table.
  • Updated "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table for presets to TX De-emphasis mappings.
  • Updated x4 Configuration and x4 Alternate Configuration figures in the "Master Channel in Bonded Configurations section".
  • Updated "PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate" section.
  • Updated “Connection Guidelines for a PIPE Gen3 Design” figure.
  • Added recommendations in the “How to Implement PCI Express (PIPE) in Arria 10 Transceivers” section.
  • Updated description of parameter “PCS TX channel bonding master” in the “Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA” table.
  • Added table “Parameter Settings for Arria 10 fPLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “fPLL IP Parameter Settings for PIPE” section.
  • Added table “Parameters for Arria 10 ATX PLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “ATX PLL IP Parameter Settings for PIPE” section.
  • Updated description of port pipe_tx_elecidle in the “Ports for Arria 10 Transceiver Native PHY in PIPE Mode” table.
  • Updated description of port pipe_tx_compliance in the “Ports for Arria 10 Transceiver Native PHY in PIPE Mode” table.
  • Updated description of port pipe_g3_txdeemph[17:0] in the “Ports for Arria 10 Transceiver Native PHY in PIPE Mode” table.
  • Added table “fPLL Ports for PIPE” in the section “fPLL Ports for PIPE” section.
  • Added table” ATX PLL Ports for PIPE “ in the “ATX PLL Ports for PIPE” section.
  • Added table “Arria 10 Preset Mappings to TX De-emphasis” in the “Preset Mappings to TX De-emphasis” section.
  • Updated figure “Alternate Configuration” figure in the “How to Place Channels for PIPE Configurations” section.
  • Updated the “PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate” section.

Made the following changes to the Other Protocols section:

  • Added the "Enhanced PCS FIFO Operation" section.
  • Changed the minimum data rate from 960 Mbps to 1.0 Gbps in the "General and Datapath Parameters" table.
2015.05.11

Made the following changes to the 10GBASE-KR PHY IP Core section:

  • Changed the register definitions for word address 0x4D0 in the "10GBASE-KR PHY Register Definitions" section.

Made the following changes to the 10GBASE-R section:

  • Added a parameter to the "RX PMA Parameters" table.

Made the following changes to the 10GBASE-KR PHY IP Core section:

  • Changed the following bits and descriptions in the "10GBASE-KR PHY Register Definitions" section:
    • Changed the bit and description for address 0x4D0[21:20].
    • Added address 0x4D0[22].
    • Removed address 0x4D0[26:24].
    • Added address 0x4D0[28:24].
    • Removed addresses 0x4D0[27] and 0x4D0[28].

Made the following changes to the Interlaken section:

  • Added available preset variations to the "Interlaken" and "How to Implement Interlaken in Arria 10 Transceivers" sections.
  • Updated the values for some parameters in the "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters", "Interlaken Frame Generator Parameters", and "Interlaken Frame Synchronizer Parameters" tables.

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

  • Changed the product ID in the "1G/10GbE Release Information" table.
  • Changed the descriptions in the "Clock and Reset Signals" table.
  • Removed the following bits from address 0x4D0 in the "Register Definitions" table:
    • 19:18
    • 26:24
    • 27

Made the following changes to the PCI Express section:

  • Updated the "Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations", "PIPE Gen1/Gen2/Gen3 Configurations", "PCIe Reverse Parallel Loopback Mode Datapath", and "Signals and Ports of Native PHY IP for PIPE" figures.
  • Updated "Rate Switch" Gen3 features.
  • Updated the "Enable simplified interface" and "Provide separate interface for each channel" parameters in the "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes" table.
  • Updated the "PCS TX channel; bonding master" parameters in the table "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA" table.
  • Updated the "Selected CDR reference clock frequency" parameter in the "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMA" table.
  • Updated "How to place channels for PIPE configurations" section to include placement guidelines for using Arria 10 PCIe Hard IP.

Made the following changes to the CPRI section:

  • Updated the "Connection Guidelines for a CPRI PHY Design" figure.
  • Added table for the "Behavior of word aligner status signals for varying interface widths", when in Manual Mode.

Made the following changes to the Other Protocols section:

  • Updated the "Connection Guidelines for a PCS Direct PHY Design" figure.
  • Updated the "Connection Guidelines for an Enhanced PCS in Low Latency Mode Design" figure.
  • Updated the description following the "Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion" figure.
  • Added a Note to the "TX Bit Slip" section.
  • Changed the value for rx_parallel_data in the "TX Bit Slip in 8-bit Mode" and "TX Bit Slip in 16-bit Mode" figures.

Made the following changes to the XAUI PHY IP Core section:

  • Removed the set_max_skew constraint from the "XAUI PHY Timing Analyzer SDC Constraints" section.

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:

  • Updated the figure for Transceiver Native PHY IP Core Parameter Editor.
  • PMA parameters
    • Updated the PMA parameter categorization in the TX PMA and RX PMA "Equalization" section.
    • Added parameters Enable tx_pma_iqtxrx_clkout port and Enable tx_seriallpbken port in "TX PMA Optional Ports" table.
    • Added parameters Enable rx_pma_iqtxrx_clkout port in "RX PMA Optional Ports" table.
    • Updated "RX PMA Parameters" table into "RX CDR Options" and "Equalization" sections.
    • Removed the option Enable rx_pma_div_clkout division factor from RX PMA optional ports table.
    • Updated the description of "CTLE Adaptation Mode" and "DFE Adaptation Mode" in "RX PMA" parameter table.
    • Updated value and description for parameter Enable tx_pma_clkout port and Enable tx_pma_div_clkout port in "TX Bonding Options" table.
    • Updated value and description for parameter Enable rx_pma_clkout port and Enable rx_pma_div_clkout port in "RX PMA Optional Ports" table.
2014.12.15

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:

  • Updated the description of tx_cal_busy and rx_cal_busy signals in the PMA Ports section.
  • Added a new section Enhanced PCS TX and RX Control Ports to better describe the tx_control and rx_control bit encodings used for different protocols. Removed the bit encodings for tx_control and rx_control signals from Enhanced PCS Ports section.
  • Updated the clock domain information about signals mentioned in Enhanced PCS Ports section.
  • Updated the description of rx_std_wa_patternalign signal in Standard PCS Ports section.
  • Updated the parameter descriptions in General Datapath Parameters and PMA Parameters sections.
  • Updated the port descriptions in PMA Ports section.

Made the following changes to the Interlaken section:

  • Added another value to the "TX channel bonding mode" parameter in the "TX PMA Parameters" table.
  • Added values to the "PCS TX channel bonding master" and "Actual PCS TX channel bonding master" parameters in the "TX PMA Parameters" table.
  • Corrected the values to the "CTLE adaptation mode" parameter in the "RX PMA Parameters" table.
  • Added the "Enable Interlaken TX random disparity bit" parameter to the "Interlaken Disparity Generator and Checker Parameters" table.
  • Changed the values to four parameters to "Off" in the "Gearbox Parameters" table.
  • Removed the "Enable embedded debug" parameter from the "Dynamic Reconfiguration Parameters" table.

Made the following changes to the Gigabit Ethernet (GbE) and GvE with IEEE 1588v2 section:

  • Added a figure description to the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.

Made the following changes to the 10GBASE-R section:

  • Added a figure description to the "Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.

Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:

  • Changed the "10GBASE-KR PHY IP Core Block Diagram" figure to activate the Standard TX PCS, Standard RX PCS, and GbE PCS blocks.
  • Added a note to the "10GBASE-KR Functional Description" section.
  • Added new parameters to the "General Options" table.
  • Changed the default values for VPOSTRULE, VPRERULE, INITPOSTVAL, and INITPREVAL in the "Optional Parameters" table.
  • "10GBASE-KR PHY Register Definitions" table:
    • Changed the default value for register address 0x4D0[7:4]
    • Changed the default value for register address 0x4D0[17].
    • Changed the descriptions for register address 0x4B2.
    • Changed the descriptions for register addresses 0x4D5 and 0x4D6.
  • Changed the descriptions for the following signals in the in the "Clock and Reset Signals" table.
    • tx_pma_clkout
    • rx_pma_clkout
    • tx_pma_div_clkout
    • rx_pma_div_clkout
  • Changed the descriptions for the following signals in the in the "XGMII Signals" table.
    • xgmii_tx_clk
    • xgmii_rx_clk
  • Removed the 1588 Soft FIFOs block from the "PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G) Ethernet Channels" figure

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

  • Changed the descriptions for register address 0x4D5 in the "1G/10GbE Register Definitions" table.
  • Removed the Daisy Chain and μP I/F lines from the Link Training block in the "1G/10GbE PHY Block Diagram" figure.
  • Changed the descriptions for 0x494 and 0x495, and added 0x4a4 bit 4 to the "GMII PCS Registers" section.

Made the following changes to the XAUI section:

  • Added a PMA width requirement in the "Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration" section.
  • Changed the figure description for the "Transceiver Clocking for XAUI Configuration" figure.
  • Changed the note in the "Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration" section.
  • Added a note to the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled" figure.
  • Added the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled" figure.
  • Removed the Data rate parameter from the "General Options" table.
  • Removed the tx_digitalreset signal from the "Clock and Reset Signals" table.
  • Changed the available signals in the "PMA Channel Controller Signals" table.
  • Added the Enable phase compensation FIFO parameter to the "Advanced Options" table.
  • Added the pll_cal_busy_i signal to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
  • Added the xgmii_rx_inclk port to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
  • Changed the description in the "Clock and Reset Signals" table.
  • Removed the following signals from the "PMA Channel Controller Signals" table:
    • tx_bonding_clocks[5:0]
    • pll_cal_busy_i
    • pll_powerdown_o
    • pll_locked_i
  • Made the following changes to the "XAUI PHY IP Core Registers" table.
    • Removed cal_blk_powerdown
    • Removed pma_tx_pll_is_locked
    • Removed Word Addresses 0x082, 0x083, 0x086, 0x087, 0x088, 0x089
    • Removed patterndetect[7:0]
    • Changed the description for syncstatus [7:0]
  • Added the xgmii_rx_inclk port to the "SDR RX XGMII Interface " table.
  • Added the pll_cal_busy_i port to the "PMA Channel Controller Signals" table.
  • Added the "XAUI PHY Timing Analyzer SDC Constraint" section.

Made the following changes to the PCI Express section:

  • Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection.
  • Updated the Rate Switch Change figure.
  • Updated the Bit Mappings When the Simplified Interface Is Disabledtable.
  • Updated the figures in How to Place Channels for PIPE Configurations.
  • Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA table.
  • Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.
  • Updated the Ports for Arria 10 Transceiver Native PHY in PIPE Mode table.
  • Updated Logical PCS Master Channel for PIPE Configuration table.
  • Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2 features with input signal name.
  • Updated the Rate Switch Change figure.
  • Updated the Gearbox Gen3 Transmission signals in the Gen3 Data Transmission figure.
  • Updated the PIPE Design Example section.
  • Updated the Gen3 Power State Management P1 to P0 Transition signals.
  • Updated the Supported Features for PIPE Configurations table.
  • Updated the Gen1/Gen2 Features section.

Made the following changes to the CPRI section:

  • Updated the parameter values for “RX word aligner mode”.
  • Added a new option for Interlaken in the GUI "Enable Interlaken TX random disparity bit".
  • For PMA configuration rules changed the option “SATA” to “SATA/SAS”.
  • Changed the GUI option “CTLE adaptation mode” to “DFE adaptation mode”.

Made the following changes to the Other Protocols section:

  • Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity Inversion".
  • Changed the initial value of tx_parallel_data in the "Manual Mode when the PCS-PMA Interface Width is 10 Bits" and "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figures.
  • Changed the minimum value for the "Data rate" parameter to 1 Gbps in the "General and Datapath Options Parameters" table.

Made the following changes to the Simulating the Native Transceiver PHY section:

  • In the introductory section, removed the third bullet in the list of netlists you can simulate because gate-level timing simulation is no longer supported.
  • Removed mention of the ModelSim DE simulator in the "How to Use NativeLink to Specify a ModelSim Simulation" section.
2014.10.08

Made the following changes to the Ethernet section:

  • Changed the frequency for mgmt_clk in the " Avalon® Memory-Mapped Interface Signals" table for Document Version10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core.

Made the following changes to the Other Protocols section:

  • Removed an erroneous note regarding Quartus® II software legality check restrictions.
2014.08.15

Made the following changes to the Transceiver Design Flow section:

  • Added "Make Pin Assignments Using Pin Planner and Assignment Editor" block to figure "Transceiver Design Flow"
  • Updated Select and Instantiate PHY IP, Generate PHY IP, Select and Instantiate PLL IP, and Generate PLL IP sections to indicate the new IP instantiation flow per ACDS 14.0A10 release.
  • Added a new section for Make Pin Assignments Using Pin Planner and Assignment Editor

Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:

  • Updated table "Arria 10 Transceiver Protocols and PHY IP Support"
    • Removed SFIS and 10G SDI from the table.
    • Updated Protocol Preset, Transceiver Configuration Rule, and PCS Support for protocols in the table.

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP section:

  • Updated references of MegaWizard Plug-In Manager to IP Catalog and Parameter Editor.
  • Added PCS Direct block in figure "Transceiver Native PHY IP Top Level Interfaces and Functional Blocks".
  • Updated figure "Transceiver Native PHY IP GUI" for 14.0A10 release IP GUI.
  • Updated General and Datapath Parameters section
    • Updated parameter descriptions in table "General and Datapath Options".
    • Updated parameter descriptions in table "Transceiver Configuration Rule Parameters".
  • Updated PMA Parameters section
    • Updated parameter descriptions in tables "TX PMA Bonding options", "TX PLL Options", "RX PMA Parameters".
    • Added description for CTLE adaptation mode and updated description for DFE adaptation mode.
  • Enhanced PCS Parameters section
    • Added a new table "Enhanced PCS Parameters"
    • Updated the parameter descriptions in tables "Enhanced PCS TX FIFO Parameters", "Enhanced PCS RX FIFO Parameters", "Interlaken Frame Generator Parameters", "Interlaken Frame Synchronizer Parameters", "10GBASE-R BER Checker Parameters", "Scrambler-Descrambler Parameters", "Block Synchronizer Parameters", "Gearbox Parameters".
    • Added descriptions in "KR-FEC Parameters" table.
  • Standard PCS Parameters
    • Updated the descriptions in tables "TX and RX FIFO Parameters", "Rate Match FIFO Parameters", "Word Aligner and Bitslip Parameters", and "PCIe Ports".
  • Dynamic Reconfiguration Parameters
    • Removed Enable Embedded JTAG Avalon-MM Master parameter and added Native PHY Debug Master Endpoint parameter and updated its description.
    • Added a table for "Embedded Debug Parameters".
  • Updated the figure "Directory Structure for Generated Files" in IP Core File Locations section.
  • Changed "one-time" to "triggered" adaptation mode for DFE and CTLE.

Made the following changes to the Interlaken section:

  • Changed parameter name in the "Signals and Ports of Native PHY IP for Interlaken" figure from tx_bonding_clock to tx_bonding_clock[5:0].
  • Updated tables in the "Native PHY IP Parameter Settings for Interlaken" section:
    • Added new tables: "10GBASE-R BER Checker Parameters", "KR-FEC Parameters".
    • Deleted table: "Configuration Profiles Parameters".
    • Added new parameters and updated existing ones to tables: "General and Datapath Parameters", "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters", "Dynamic Reconfiguration Parameters".
    • Updated existing parameters to tables: "Interlaken Frame Generator Parameters", "Interlaken CRC-32 Generator and Checker Parameters".

Made the following changes to the Ethernet section:

  • Initial release of the XAUI PHY IP Core section.
  • Changed the bus width between the FPGA fabric and PCS, and added notes 3 and 4 to the "Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.
  • Provided the full hexadecimal values for rx_parallel_data, rx_patterndetect, and rx_runningdisp in the "Decoding for GbE" figure description.
  • Changed the note in the Rate Match FIFO for GbE section to clarify the case where 200 ppm total is valid.
  • Added the pll_cal_busy circuitry, updated signals, and added a note to the "Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design" figure.
  • Removed the Device and speed grade parameter from the "General and Datapath Options" table.
  • Changed the values for the PPM detector threshold parameter and removed the Decision feedback equalization parameter in the "RX PMA Parameters" table.
  • Changed the 10GBASE-R PHY grouping in the "10GBASE-R PHY as Part of the IEEE802.3-2008 Open System Interconnection (OSI)" figure.
  • Added that 10GBASE-R is compatible with the 10-Gbps Ethernet MAC Intel® FPGA IPCore Function in the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants section.
  • Added the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2" figure.
  • Changed steps 1 and 4 in the How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers section to match the GUI.
  • Specified the target BER of 10-12 in the 10GBASE-KR PHY IP Core section.
  • Removed the "Top Level Modules of the 1G/10GbE PHY Intel® FPGA IP Core Function" figure.
  • Removed the 10GBASE-KR PHY with 1588 variant from the "10GBASE-KR PHY Performance and Resource Utilization" table. This is not supported.
  • Replaced the "10GBASE-KR PHY IP Block Diagram" figure.
  • Added the Auto Negotiation, IEEE 802.3 Clause 73 section.
  • Substantially rewrote the Link Training (LT), IEEE 802.3 Clause 72 section.
  • Removed the "TX Equalization for Link Partners" figure.
  • Removed the "TX Equalization in Daisy Chain Mode" figure. Daisy chain is not supported.
  • Removed the Auto Negotiation section.
  • Replaced the "Reconfiguration Block Details" figure.
  • Removed the Initial Datapath, Enable internal PCS reconfiguration logic, and Enable IEEE 1588 Precision time Protocol parameters from the "General Options Parameters" table.
  • Added the Reference clock frequency, Enable additional control and status pins, Include FEC sublayer, Set FEC_ability bit on power up and reset, and Set FEC_Enable bit on power up and reset parameters to the "General Options Parameters" table.
  • Removed the 10GBASE-R Parameters section.
  • Removed the 10M/100M/1Gb Ethernet Parameters section.
  • Removed the Speed Detection Parameters section.
  • Substantially changed the "Auto Negotiation and Link Training Settings" table, adding the AN_PAUSE Pause Ability, CAPABLE_FEC ENABLE_FEC (request), AN_TECH Technology Ability, AN_SELECTOR Selector Field, and Width of the Training Wait Counter parameters.
  • Updated all parameter names, values, and descriptions in the "Optional Parameters" table.
  • Updated the signals in the "10GBASE-KR Top-Level Signals" figure.
  • Removed the rx_serial_clk_1g and tx_serial_clk_1g signals, and removed all references to "1G" from all descriptions in the "Clock and Reset Signals" table.
  • Removed references to GMII and MII interfaces from the Data Interfaces section.
  • Removed GMII and MII signals from the "XGMII Signals" table.
  • Updated the list of signals in the "Control and Status Signals" table.
  • Removed the Daisy-Chain Interface Signals section.
  • Removed the Embedded Processor Interface Signals section.
  • Updated the list of signals in the "Dynamic Reconfiguration Interface Signals" table.
  • Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register Definitions" table.
  • Updated the 0x482 registers in the "PCS Registers" table.
  • Updated and removed some addresses in the "PMA Registers" table.
  • Added the Speed Change Summary section.
  • Removed the 10GBASE-KR, Backplane, FEC, GMII PCS Registers section.
  • Removed the 1588 Delay Requirement section.
  • Removed the Channel Placement Guidelines section.
  • Removed the introductory paragraph from the Design Example section.
  • Removed the 1588 FIFO block from the "Top Level Modules of the 1G/10GbE PHY Intel® FPGA IP Core Function" figure.
  • Updated all values for ALMs, ALUTs, Registers, and M20K in the "1G/10GbE PHY Performance and Resource Utilization" table.
  • Updated the blocks in the "Reconfiguration Block Details" figure.
  • Changed the blocks and clock connections in the "Clocks for Standard and 10G PCS and TX PLLs" figure.
  • Changed signal names and descriptions in the "Clock and Reset Signals" table.
  • Changed the parameter name for 10GbE Reference Clock frequency and added the 1G Reference clock frequency parameter in the "10GBASE-R Parameters" table.
  • Removed the Set FEC_ability bit on power up and reset and Set FEC_enable bit on power up and resetparameters from the "FEC Options" table.
  • Updated the list of available signals in the "1G/10GbE PHY Top-Level Signals" figure.
  • Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register Definitions" table.
  • Added the 0x4A8 and 0x4A9 addresses and updated the name for address 0x4A2 and 0x4A3 in the "10GBASE-KR, Backplane, FEC GMII PCS Registers" table.
  • Added the Speed Change Summary section.

Made the following changes to the PCI Express section:

  • Added a new topic Pipe link equalization for Gen 3 data rate.
  • Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Connect TX PLLs for PIPE Gen1, Gen2 and Gen3 Mode section.
  • Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Implement PCI Express in Arria 10 Transceivers section.
  • Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the Supported Pipe Features section.

Made the following changes to the CPRI section:

  • Added new values to each row in the "TX PLL Supported Data Rates" table.

Made the following changes to the Other Protocols section:

  • Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
  • Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
  • Changed references from MegaWizard to IP Catalog or Parameters Editor.
  • Using the Basic and Basic with KR FEC Configurations of Enhanced PCS
    • Updated the "Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) Configuration" figure and added footnote 3.
    • Updated the "General and Datapath Parameters", "TX PMA Parameters", "RX PMA Parameters", and "Enhanced PCS Parameters" tables.
    • Added the "Equalization" table.
    • Added the "How to Enable Low Latency in Basic Enhanced PCS" section.
  • Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS
    • Updated the values in the "Manual Mode when the PCS-PMA Interface is 8 Bits", "Manual Mode when the PCS-PMA Interface is 10 Bits", and "Manual Mode when the PCS-PMA Interface is 16 Bits" figures.
    • Added the "8B/10B Encoder and Decoder" and "8B/10B TX Disparity Control" sections.
    • Updated the "Connection Guidelines for a Basic/Custom Design" figure.
    • Updated the "General and Datapath Options Parameters", "TX PMA Parameters", "RX PMA Parameters", and "Standard PCS Parameters" tables.
  • Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels
    • Updated the maximum data rate for GT channels to 25.4 Gbps.
    • Added information about PCS Direct mode.
    • Updated "ATX PLL IP with GT Clock Lines Enabled" figure.
  • Updated the How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria 10 Transceivers section.

Made the following changes to the Simulating the Transceiver Native PHY IP Core section:

  • Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
  • Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
2013.12.02 Initial release.
Level Two Title