Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.17. Timing Closure Recommendations

Intel recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP core if any of the modified or target configurations involve changes to PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as PLL switching, CGB divider switching, and refclk switching. When you enable multiple reconfiguration profiles, the Quartus Prime TimeQuest Timing Analyzer includes the necessary PCS timing arcs for all profiles (initial profile and target profiles) during timing driven compilation. These timing arcs make the timing more accurate.

When performing a dynamic reconfiguration, you must:

  • Include constraints to create the extra clocks for all modified or target configurations at the PCS-FPGA fabric interface. Clocks for the base configuration are created by the Quartus Prime software. These clocks enable the Quartus Prime software to perform static timing analysis for all the transceiver configurations and their corresponding FPGA fabric core logic blocks.
  • Include the necessary false paths between the PCS – FPGA fabric interface and the core logic.

For example, you can perform dynamic reconfiguration to switch the datapath from Standard PCS to Enhanced PCS using the multiple reconfiguration profiles feature. In the following example, the base configuration uses the Standard PCS (data rate = 1.25 Gbps, PCS-PMA width = 10) and drives core logic A in the FPGA fabric. The target or modified configuration is configured to use the Enhanced PCS (data rate = 12.5 Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.

Figure 282. Using Multiple Reconfiguration Profiles

To enable the Quartus Prime software to close timing more accurately in this example, the following constraints must be created:

  • create_clock -name tx_clkout_enh -period 5.12 [get_pins {native_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pcs_tx_clk_out}] -add

    This constraint creates the tx_clkout clock that is used to clock the core logic B in the FPGA fabric.

  • create_clock -name rx_clkout_enh –period 5.12 [get_pins {native_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pcs_rx_clk_out}] -add

    This constraint creates the rx_clkout clock that is used to clock the core logic B in the FPGA fabric.

  • set_false_path -from [get_clocks {tx_clkout_enh}] -to [get_registers <Core Logic A>]

    Based on how the clocks are connected in the design, you might have to include additional constraints to set false paths from the registers in the core logic to the clocks.

  • set_false_path -from [get_clocks {rx_clkout_enh}] -to [get_registers <Core Logic A>]

    Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.

  • set_false_path -from [get_clocks {tx_clkout}] -to [get_registers <Core Logic B>]

    Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.

  • set_false_path -from [get_clocks {rx_clkout}] -to [get_registers <Core Logic B>]

    Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.

    Note: If any of the profile or configuration switch involves switching from FIFO to the register mode, then the false paths should be set between the PCS-PMA interface register and the core logic because the common clock point is within the PCS-PMA interface.

For example, if the base configuration of the above case is configured for the TX and RX FIFOs in the Register Mode, the following constraint needs to be created:

  • set_false_path -from [get_registers {native:native_inst|native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pma_tx_pma_clk_reg.reg}] -to [get_registers <Core Logic B>]
  • set_false_path -from [get_registers {native:native_inst|native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface~pma_rx_pma_clk_reg.reg}] -to [get_registers <Core Logic B>]
Note: When the dynamic reconfiguration (multi profiles) is enabled, do not move or rename the IP directory. Moving the IP location causes Quartus to fail to pick up the configuration profiles. If the IP directory is changed, the default configuration can be successfully time constrained and analyzed, but the non-default configuration has timing issues as the timing arc may be missing.

Did you find the information on this page useful?

Characters remaining:

Feedback Message