Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.1. Reconfiguring Channel and PLL Blocks

The following table lists some of the available dynamic reconfiguration features in Arria® 10 devices.

Table 262.   Arria® 10 Dynamic Reconfiguration Feature Support
Reconfiguration Features
Channel Reconfiguration PMA analog features
  • VOD
  • Pre-emphasis
  • Continuous Time Linear Equalizer (CTLE)
  • Decision Feedback Equalization (DFE)
TX PLL
  • TX local clock dividers
  • TX PLL switching
RX CDR
  • RX CDR settings
  • RX CDR reference clock switching
Reconfiguration of PCS blocks within the datapath
Datapath switching
  • Standard, Enhanced, PCS Direct
PLL Reconfiguration PLL settings
  • Counters
PLL reference clock switching

Did you find the information on this page useful?

Characters remaining:

Feedback Message