Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.9. Enhanced PCS Ports

Figure 24. Enhanced PCS InterfacesThe labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 48.  Enhanced TX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description

tx_parallel_data[<n>128-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified interface in the Transceiver Native PHY IP Parameter Editor, tx_parallel_data includes only the bits required for the configuration you specify.

You must ground the data pins that are not active. For single width configuration, the following bits are active:

  • 32-bit FPGA fabric to PCS interface width: tx_parallel_data[31:0]. Ground [127:32].
  • 40-bit FPGA fabric to PCS interface width: tx_parallel_data[39:0]. Ground [127:40].
  • 64-bit FPGA fabric to PCS interface width: tx_parallel_data[63:0] Ground [127:64].

For double width configuration, the following bits are active:

  • 40-bit FPGA fabric to PCS interface width: data[103:64], [39:0]. Ground [127:104], [63:40].
  • 64-bit FPGA fabric to PCS interface width: data[127:64], [63:0].

Double-width mode is not supported for 32-bit, 50-bit, and 67-bit FPGA fabric to PCS interface widths.

unused_tx_parallel_data

Input

tx_clkout Port is enabled, when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a part of tx_parallel_data. Refer to tx_parallel_data to identify the bits you need to ground.
tx_control[<n><3>-1:0] or

tx_control[<n><18>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

tx_control bits have different functionality depending on the transceiver configuration rule selected. When Simplified data interface is enabled, the number of bits in this bus change because the unused bits are shown as part of the unused_tx_control port.

Refer to Enhanced PCS TX and RX Control Ports section for more details.

unused_tx_control[<n> <15>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

This port is enabled when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a part of the tx_control.

Refer to tx_control to identify the bits you need to ground.

tx_err_ins Input tx_coreclkin

For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on Enable simplified data interface.

When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe.

Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP GUI.

tx_coreclkin[<n>-1:0] Input Clock

The FPGA fabric clock. Drives the write side of the TX FIFO. For the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption.

tx_clkout[<n>-1:0]

Output

Clock

This is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX Enhanced PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width.

Table 49.  Enhanced RX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description

rx_parallel_data[<n>128-1:0]

Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver Native PHY IP GUI, rx_parallel_data includes only the bits required for the configuration you specify. Otherwise, this interface is 128 bits wide.

When FPGA fabric to PCS interface width is 64 bits, the following bits are active for interfaces less than 128 bits. You can leave the unused bits floating or not connected.

  • 32-bit FPGA fabric to PCS width: data[31:0].
  • 40-bit FPGA fabric to PCS width: data[39:0].
  • 64-bit FPGA fabric to PCS width: data[63:0].

When the FPGA fabric to PCS interface width is 128 bits, the following bits are active:

  • 40-bit FPGA fabric to PCS width: data[103:64], [39:0].
  • 64-bit FPGA fabric to PCS width: data[127:0].
unused_rx_parallel_data

Output

rx_clkout

This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_parallel_data. You can leave the unused data outputs floating or not connected.
rx_control[<n> <20>-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

Indicates whether the rx_parallel_data bus is control or data.

Refer to the Enhanced PCS TX and RX Control Ports section for more details.

unused_rx_control[<n>10-1:0] Output

Synchronous to the clock driving the read side of the FIFO (rx_coreclkin or rx_clkout)

These signals only exist when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_control. These outputs can be left floating.
rx_coreclkin[<n>-1:0] Input Clock

The FPGA fabric clock. Drives the read side of the RX FIFO. For Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32.

rx_clkout[<n>-1:0]

Output

Clock

The low speed parallel clock recovered by the transceiver RX PMA, that clocks the blocks in the RX Enhanced PCS. The frequency of this clock is equal to data rate divided by PCS/PMA interface width.

Table 50.  Enhanced PCS TX FIFO
Name Direction Clock Domain Description
tx_enh_data_valid[<n>-1:0]

Input

Synchronous to the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Assertion of this signal indicates that the TX data is valid. Connect this signal to 1'b1 for 10GBASE-R without 1588. For 10GBASE-R with 1588, you must control this signal based on the gearbox ratio. For Basic and Interlaken, you need to control this port based on TX FIFO flags so that the FIFO does not underflow or overflow.

Refer to Enhanced PCS FIFO Operation for more details.

tx_enh_fifo_full[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO tx_coreclkin.

The clock driving the write side of TX FIFO can be tx_coreclkin (FPGA fabric clock) or tx_clkout.

Assertion of this signal indicates the TX FIFO is full. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_enh_fifo_pfull[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO tx_coreclkin.

The clock driving the write side of TX FIFO can be tx_coreclkin (FPGA fabric clock) or tx_clkout.

This signal gets asserted when the TX FIFO reaches its partially full threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_enh_fifo_empty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO tx_clkout

When asserted, indicates that the TX FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

tx_enh_fifo_pempty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO tx_clkout

When asserted, indicates that the TX FIFO has reached its specified partially empty threshold. When you turn this option on, the Enhanced PCS enables the tx_enh_fifo_pempty port, which is asynchronous. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

Table 51.  Enhanced PCS RX FIFO
Name Direction Clock Domain Description
rx_enh_data_valid[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data whenrx_enh_data_valid signal is low.

This option is available when you select the following parameters:

  • Enhanced PCS Transceiver configuration rules specifies Interlaken
  • Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Phase compensation
  • Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Register

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_fifo_full[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO rx_clkout

When asserted, indicates that the RX FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_fifo_pfull[<n>-1:0]

Output

Synchronous to the clock driving the write side of the FIFO rx_clkout

When asserted, indicates that the RX FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_fifo_empty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin.

The clock driving the read side of RX FIFO can be rx_coreclkin (FPGA fabric clock) or rx_clkout.

When asserted, indicates that the RX FIFO is empty. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_fifo_pempty[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin.

The clock driving the read side of RX FIFO can be rx_coreclkin (FPGA fabric clock) or rx_clkout.

When asserted, indicates that the RX FIFO has reached its specified partially empty threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation for more details.

rx_enh_fifo_del[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that a word has been deleted from the RX FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol.

rx_enh_fifo_insert[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that a word has been inserted into the RX FIFO. This signal is used for the 10GBASE-R protocol.

rx_enh_fifo_rd_en[<n>-1:0]

Output

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

For Interlaken only, when this signal is asserted, a word is read form the RX FIFO. You need to control this signal based on RX FIFO flags so that the FIFO does not underflow or overflow.
rx_enh_fifo_align_val[<n>-1:0]

Input

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, indicates that the word alignment pattern has been found. This signal is only valid for the Interlaken protocol.

rx_enh_fifo_align_clr[<n>-1:0]

Input

Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout

When asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles.

Table 52.  Interlaken Frame Generator, Synchronizer, and CRC32
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0] Output

tx_clkout

Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe.

tx_enh_frame_diag_status[<n> 2-1:0]

Input

tx_clkout

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the frame generator block. This bus must be held constant for 5 clock cycles before and after the tx_enh_frame pulse. The following encodings are defined:

  • Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.
  • Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
tx_enh_frame_burst_en[<n>-1:0]

Input

tx_clkout

If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each Metaframe. If the value of tx_enh_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts SKIP words as the payload of Metaframe. When tx_enh_frame_burst_en is 1, the frame generator reads data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the tx_enh_frame pulse.

rx_enh_frame[<n>-1:0]

Output

rx_clkout

When asserted, indicates the beginning of a new received Metaframe. This signal is pulse stretched.

rx_enh_frame_lock[<n>-1:0]

Output

rx_clkout

When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched.

rx_enh_frame_diag_status[2 <n>-1:0]

Output

rx_clkout

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined:

  • Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.
  • Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
rx_enh_crc32_err[<n>-1:0]

Output

rx_clkout

When asserted, indicates a CRC error in the current Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles.

Table 53.  10GBASE-R BER Checker
Name Direction Clock Domain Description
rx_enh_highber[<n>-1:0] Output

rx_clkout

When asserted, indicates a bit error rate that is greater than 10 -4. For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs. This signal gets asserted for 2 to 3 clock cycles.

rx_enh_highber_clr_cnt[<n>-1:0]

Input

rx_clkout

When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state.
rx_enh_clr_errblk_count[<n>-1:0] (10GBASE-R and FEC)

Input

rx_clkout

When asserted the error block counter resets to 0. Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the RX_E state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block.

Table 54.  Block Synchronizer
Name Direction Clock Domain Description
rx_enh_blk_lock<n>-1:0] Output

rx_clkout

When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for 10GBASE-R and Interlaken.
Table 55.  Gearbox
Name Direction Clock Domain Description
rx_bitslip[<n>-1:0] Input

rx_clkout

The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. Keep the minimum interval between rx_bitslip pulses to at least 20 cycles. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.

tx_enh_bitslip[<n>-1:0] Input rx_clkout

The value of this signal controls the number of bits to slip the tx_parallel_data before passing to the PMA.

Table 56.  KR-FEC
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0] Output

tx_clkout

Asynchronous status flag output of TX KR-FEC that signifies the beginning of generated KR FEC frame
rx_enh_frame[<n>-1:0] Output rx_clkout Asynchronous status flag output of RX KR-FEC that signifies the beginning of received KR FEC frame
rx_enh_frame_diag_status Output rx_clkout

Asynchronous status flag output of RX KR-FEC that indicates the status of the current received frame.

  • 00: No error
  • 01: Correctable Error
  • 10: Un-correctale error
  • 11: Reset condition/pre-lock condition

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