Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine

In Arria 10 devices, calibration is performed using the Precision Signal Integrity Calibration Engine (PreSICE). The PreSICE includes an Avalon® memory-mapped interface to access the transceiver channel and PLL programmable registers. This Avalon® memory-mapped interface includes a communication mechanism that enables you to request specific calibration sequences from the calibration controller.

The PreSICE Avalon® memory-mapped interface and user Avalon® memory-mapped interface reconfiguration both share an internal configuration bus. This bus is arbitrated to gain access to the transceiver channel and PLL programmable registers, and the calibration registers.

There are two ways to check who has the access to the internal configuration bus:

  • Use reconfig_waitrequest
  • Use capability registers

The Native PHY IP core and PLL default setting is to use reconfig_waitrequest. When PreSICE controls the internal configuration bus, the reconfig_waitrequest from the internal configuration bus is high. When user access is granted, the reconfig_waitrequest from the internal configuration bus goes low. At the Avalon® memory-mapped interface reconfiguration, the reconfig_waitrequest can come from a few places inside Native PHY IP core. For example, it can come from the internal configuration bus, streamer, and so on. They are bundled together and become single reconfig_waitrequest at the Avalon® memory-mapped interface reconfiguration. The reconfig_address determines which reconfig_waitrequest to show at the Avalon® memory-mapped interface reconfiguration. After you return the internal configuration bus to PreSICE, the reconfig_waitrequest from the internal configuration bus is high. If you set the reconfig_address to the streamer offset address at the Avalon® memory-mapped interface reconfiguration during calibration, the reconfig_waitrequest can be low before calibration is finished. If you keep the reconfig_address the same as the internal configuration bus offset address during calibration, the reconfig_waitrequest at the Avalon® memory-mapped interface reconfiguration is high until PreSICE returns the internal configuration bus to you. It is important to keep reconfig_address static during calibration.

To use capability registers to check bus arbitration, you do the following to generate the IP:

  1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration tab.
  2. Select both the Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE and Enable control and status registers options.

You can read the capability register 0x281[2] to check who is controlling the channel access, and read the capability register 0x280[2] to check who is controlling the PLL access. When Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE and Enable control and status registers are enabled, the reconfig_waitrequest is not asserted high when PreSICE controls the internal configuration bus.

To return the internal configuration bus to PreSICE:

  • In order to trigger user re-calibration:
    • Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request through offset address 0x100.
  • In order to trigger DFE adaptation:
    • Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through 0x100[6].
  • If you no longer need to use the internal reconfiguration bus:
    • Write 0x03 to offset address 0x000 [7:0].

To check if the calibration process is running, do one of the following:

  • Monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy signals.
  • Read the *_cal_busy signal status from the capability registers.

The *_cal_busy signals remain asserted as long as the calibration process is running. To check whether or not calibration is done, you can read the capability registers or check the *_cal_busy signals. The reconfig_waitrequest from the Avalon® memory-mapped interface reconfiguration is not a reliable indicator to check whether or not calibration is done. If you write 0x2 to 0x0 during calibration, PreSICE can stop the calibration process and return the internal configuration bus back to you; therefore, calibration is not done while the reconfig_waitrequest is low. The PMA tx_cal_busy and rx_cal_busy are from the same internal node which cannot be separated from the hardware. Configure the capability register 0x281[5:4] to enable or disable tx_cal_busy or rx_cal_busy individually through the Avalon® memory-mapped interface reconfiguration.

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