Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.3.1.1.3. TX FIFO Fast Register Mode

This mode allows a higher maximum frequency (fMAX) between the FPGA fabric and the TX PCS by enabling the optional fast register interface with additional latency.

Did you find the information on this page useful?

Characters remaining:

Feedback Message