Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Document Table of Contents RX Gearbox, RX Bitslip, and Polarity Inversion

The RX gearbox adapts the PMA data width to the larger bus width of the PCS channel (Gearbox Expansion). It supports different ratios (PCS-PMA interface width : FPGA fabric–PCS interface width) such as 32:66, 40:66, 32:67, 32:64, 40:40, 32:32, 64:64, 67:64, and 66:64 and a bit slipping feature.

RX bitslip is engaged when the RX block synchronizer or rx_bitslip is enabled to shift the word boundary. On the rising edge of the bitslip signal of the RX block synchronizer or rx_bitslip from the FPGA fabric, the word boundary is shifted by one serial bit or 1UI. Each bit slip removes the earliest received bit from the received data.

Figure 247. RX Bitslip rx_bitslip is toggled two times, which shifts the rx_parallel_data boundary two bits.