Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.3.7. Creating a 10GBASE-KR Design

Follow these steps to create a 10GBASE-KR design.
  1. Generate the 10GBASE-KR PHY with the required parameterization.
    The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration block provides the Avalon® memory-mapped interface to access the PHY registers.
  2. Instantiate a reset controller. You can generate a Transceiver Reset Controller IP core from the IP Catalog. You must connect the Transceiver Reset Controller IP core and 10GBASE-KR PHY IP core power and reset signals.
  3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate. Connect the high speed serial clock and PLL lock signals between 10GBASE-KR PHY and TX PLLs. For the 1G data rate you can use either fPLL, ATX PLL, or CMU PLL. For the 10G data rate you can use ATX PLL or CMU PLL.
  4. Generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
  5. Use the tx_pma_divclk from the 10GBASE-KR PHY or generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
    Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10 devices.
  6. Complete the design by creating a top level module to connect all the IP (10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.

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