Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.3.7. Creating a 10GBASE-KR Design

Follow these steps to create a 10GBASE-KR design.
  1. Generate the 10GBASE-KR PHY with the required parameterization.
    The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration block provides the Avalon® memory-mapped interface to access the PHY registers.
  2. Instantiate a reset controller. You can generate a Transceiver Reset Controller IP core from the IP Catalog. You must connect the Transceiver Reset Controll