Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

3.8. Unused/Idle Clock Line Requirements

Unused or idle transceiver clock lines can degrade if the devices are powered up to normal operating conditions and not configured. This affects designs that configure transceiver RX channels to use the idle clock lines at a later date by using dynamic reconfiguration or a new device programming file. Clock lines affected are unused, or idle RX serial clock lines. Active RX serial clock lines and non-transceiver circuits are not impacted by this issue.

In order to prevent the performance degradation, for idle transceiver RX channels, recompile designs with Intel® Quartus® Prime version 16.1 or later with the assignment described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not assert the analog reset signals indefinitely.

Did you find the information on this page useful?

Characters remaining:

Feedback Message