Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents fPLL Reference Clock Switching

You can use the reconfiguration interface on the fPLL instance to specify which reference clock source drives the fPLL. The fPLL supports clocking by up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the reconfiguration interface.

Before initiating a reference clock switch, ensure that your fPLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during fPLL parameterization.

The following table shows the addresses and bits for switching between fPLL reference clock inputs. The number of exposed pll_refclk ports varies according to the number of reference clocks you specify. Use the fPLL reconfiguration interface for this operation.

Table 270.  Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port Description Address Bits
pll_refclk0 Represents logical refclk0 for MUX_0. Lookup register x117[7:0] stores the mapping from logical refclk0 to the physical refclk for MUX_0. 0x117 (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_0. Lookup register x118[7:0] stores the mapping from logical refclk1 to the physical refclk for MUX_0. 0x118 (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_0. Lookup register x119[7:0] stores the mapping from logical refclk2 to the physical refclk for MUX_0. 0x119 (Lookup Register) [7:0] <